Vulnerability Analysis of L2 Cache Elements to Single Event Upsets

Abstract

Memory elements are the most vulnerable system component to soft errors. Since memory elements in cache arrays consume a large fraction of the die in modern microprocessors, the probability of particle strikes in these elements is high and can significantly impact overall processor reliability. Previous work [2] has developed effective metrics to accurately measure the vulnerability of cache memory elements. Based on these metrics, we have developed a reliability-performance evaluation framework, which has been built upon the Simplescalar simulator.In this work, we focus on the reliability aspects of L1 and L2 caches. Specifically, we present algorithms for tag vulnerability computation and investigate and report in detail on the vulnerability of data, tag, and status bits in the L2 array. Experiments on SPECint2K and SPECfp2K benchmarks show that one class of error, replacement error, makes up almost 85% of the total tag vulnerability of a 1MB write-back L2 cache. In addition, the vulnerability of L2 tag-addresses significantly increases as the size of the memory address space increases. Results show that the L2 tag array can be as susceptible as first-level instruction and data caches (IL1/DL1) to soft errors.

A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors used in Information Systems

“…The field analysis carried out in this work agrees with the findings presented in [12]. With the help of the MCA given in [17], it was observed that only 12% of the errors were found to have occurred in the LI cache.…”

“…As mentioned in [12], ECC protection reduces the effective vulnerability of the L2 data array to zero and the primary source of L2 vulnerability is the tag array. It was observed that the L2 tag vulnerability is greater than the vulnerability of LI data and Instruction cache for most of the SPEC benchmarks when a similar processor and memory organization was considered.…”

“…To further investigate the vulnerability of the L2 tag addresses, the L2 tag vulnerability was profiled in terms of pseudo-hit vulnerability, replacement vulnerability, multi-hit vulnerability, and status vulnerability in [12]. The results show that replacement vulnerability makes up almost 85% of the total tag vulnerability.…”

On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors

“…Due to their large share of the transistor budget and die area, on-chip caches suffer from an increasing vulnerability to soft errors [4]. As a critical requirement for reliable computing [5], protecting the information integrity in cache memories has captured a wealth of research efforts [5], [6], [7], [8], [9], [10], [11], [12], [13].…”

“…Such a study could provide enough insight into cache reliability behavior, which the designer could take advantage of to design highly costeffective reliable caches. Recent papers [8], [9], [10], [1], [15], [16] present some initial efforts toward such a cache vulnerability analysis. However, their cacheline-or wordbased vulnerability characterization used some simple generation model [17] that could not explore the temporal vulnerability of the cache, i.e., how different lifetime phases of the cache data contribute to vulnerability.…”