Untitled

This article presents a methodology for testing high-performance pipelined circuits with slow-speed testers. The technique uses a clock timing circuit to control data transfer in the pipeline in test mode. The technique adds no extra hardware in the data path of the pipeline and therefore has virtually no performance penalty. A clock timing circuit capable of achieving a timing resolution of 50 ps in 0.18 µm CMOS technology is presented. The design provides the ability to test the clock timing circuit itself. The effectiveness of the technique is demonstrated using a 16-bit pipelined multiplier as a test vehicle. Simulations show that we are able to detect delay faults as small as 50 ps at an input clock frequency of 100 MHz.

show abstract

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

customersupport@researchsolutions.com

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

Untitled

Cited by 2 publications

References 12 publications

Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths

Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths

Testing high-performance pipelined circuits with slow-speed testers

Contact Info

Product

Resources

About