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Lucia, Andrea De; Fasano, Fausto; Oliveto, Rocco; Tortora, Genoveffa

doi:10.1002/spe.v40:11

Cited by 16 publications

(3 citation statements)

References 152 publications

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“…As a matter of fact, modern processors integrate on-die LLCs [12] in the uncore domain, referred to as power controller systems (PCSs), as dedicated embedded hardware resources, co-designed with a power control firmware (PCF) implementing complex multiple-input multiple-output (MIMO) power management policies. Advanced DTM involves embedding and interleaving a plurality of activities in the PCS, namely (i) dynamic control of the CPU power consumption with short time constants [13], required to prevent thermal hazards and to meet the TPD limit (power capping [14]), (ii) real-time interaction with commands provided by on-die (Operating System (OS) -power management interfaces and on-chip sensors) and off-die (Baseboard Management Controller (BMC), voltage regulator modules (VRMs)) units and (iii) dynamic power budget allocation between general-purpose (CPUs) and other integrated subsystems, such as graphic processing units (GPUs) [8].…”

Section: Introductionmentioning

confidence: 99%

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

Ottaviano

Balas

Bambini

et al. 2023

Preprint

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High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate an on-die power controller system (PCS). While traditional PCSs are based on a simple microcontroller (MCU)-class core, more scalable and flexible PCS architectures are required to support advanced MIMO control algorithms for managing the ever-increasing number of cores, power states, and process, voltage, and temperature variability. This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCS platform consisting of a single-core MCU with fast interrupt handling coupled with a scalable multi-core programmable cluster accelerator and a specialized DMA engine for the parallel acceleration of real-time power management policies. ControlPULP relies on FreeRTOS to schedule a reactive power control firmware (PCF) application layer. We demonstrate ControlPULP in a power management use-case targeting a next-generation 72-core HPC processor.We first show that the multi-core cluster accelerates the PCF, achieving 4.9x speedup compared to single-core execution, enabling more advanced power management algorithms within the control hyper-period at a shallow area overhead, about 0.1\% the area of a modern HPC CPU die. We then assess the PCS and PCF by designing an FPGA-based, closed-loop emulation framework that leverages the heterogeneous SoCs paradigm, achieving DVFS tracking with a mean deviation within 3\% the plant's thermal design power (TDP) against a software-equivalent model-in-the-loop approach. Finally, we show that the proposed PCF compares favorably with an industry-grade control algorithm under computational-intensive workloads.

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Section: Introductionmentioning

confidence: 99%

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

Ottaviano

Balas

Bambini

et al. 2023

Preprint

View full text Add to dashboard Cite

show abstract

“…Hence, all modern processors integrate on-die Power Controller Subsystems as dedicated hardware resources co-designed with a Power Control Firmware (PCF) implementing complex MIMO power management policies. Advanced power management involves embedding and interleaving a plurality of activities in the PCS, namely (i) dynamic control of the CPU power consumption with short time constants [16] to prevent thermal hazards and to meet the TDP limit (power capping [11]), (ii) real-time interaction with inputs provided by on-die (Operating System -OS -power management interfaces and on-chip sensors) and off-die (Baseboard Management Controller -BMC -, Voltage Regulator Modules -VRMs -) units and (iii) dynamic power budget allocation between general-purpose (CPUs) and other integrated subsystems, such as graphics processors (GPUs) [21].…”

Section: Introductionmentioning

confidence: 99%

ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration

Ottaviano

Balas

Bambini

et al. 2022

Lecture Notes in Computer Science

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High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems requiring complex and highperformance closed-loop control strategies for efficient power and thermal management. To satisfy high-bandwidth, real-time multi-input multioutput (MIMO) optimal power control requirements, high-end processors integrate on-die Power Controller Systems (PCS). Traditional PCS is based on a simple microcontroller core supported by dedicated interface logic and sequencers. More scalable and flexible PCS architectures are required to support advanced MIMO control algorithms required for managing the ever-increasing number of cores, power states, and process, voltage, temperature (PVT) variability. In this paper, we present ControlPULP, a complete, open-source HW/SW RISC-V parallel PCS platform consisting of a single-core microcontroller coupled with a scalable multi-core cluster system with a specialized DMA engine and a fast multi-core interrupt controller for parallel acceleration of real-time power management policies. ControlPULP relies on a realtime OS (FreeRTOS) to schedule a Power Control Firmware (PCF) software layer. We evaluate ControlPULP design choices in a cycle-accurate, event-based simulation environment and show the benefits of the proposed multi-core acceleration solution. We demonstrate ControlPULP in a PCS use-case targeting a next-generation 72-cores HPC processor. We show that the multi-core cluster accelerates the PCF achieving 4.9x speedup with respect to single-core execution.

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“…Energy efficiency has been at the forefront of the highperformance computing (HPC) developments to tackle energy and power consumption crisis of HPC systems [27]. A promising approach that fulfills the DARPA's requirements [27] in designing next generation of exascale supercomputers has been heterogeneity [9,12,[15][16][17]28]; from the node-level heterogeneity like Titan [22] and Summit [21] to the chip-level heterogeneity as in the System-on-a-chip architectures [1,5]. However, developing applications for heterogeneous systems is not an easy task and requires novel approaches (e.g., directive-based programming models [6,8,10,19,20]) to assist the application developers in their efforts.…”

Section: Introductionmentioning

confidence: 99%

Assessing Performance Implications of Deep Copy Operations via Microbenchmarking

Ghane¹,

Chandrasekaran²,

Cheung³

2019

Preprint

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As scientific frameworks become sophisticated, so do their data structures. Current data structures are no longer simple in design and they have been progressively complicated. The typical trend in designing data structures in scientific applications are basically nested data structures: pointing to a data structure within another one. Managing nested data structures on a modern heterogeneous system requires tremendous effort due to the separate memory space design.In this paper, we will discuss the implications of deep copy on data transfers on current heterogeneous. Then, we will discuss the two options that are currently available to perform the memory copy operations on complex structures and will introduce pointerchain directive that we proposed. Afterwards, we will introduce a set of extensive benchmarks to compare the available approaches. Our goal is to make our proposed benchmarks a base to examine the efficiency of upcoming approaches that address the challenge of the deep copy operation.CCS Concepts • Computer systems organization → Heterogeneous (hybrid) systems; High-level language architectures;

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Untitled

Cited by 16 publications

References 152 publications

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration

Assessing Performance Implications of Deep Copy Operations via Microbenchmarking

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