Wafer level critical dimension control in spacer-defined double patterning for sub-72 nm pitch logic technology

Abstract

Fabrication of sub-100-nm metal-oxide-semiconductor field-effect transistors with asymmetrical source/drain using I-line double patterning techniqueOptimization of critical dimension (CD) uniformity during a spacer-defined double patterning process was explored. Image log-slope (ILS) was used as a major metric in optimizing the CD uniformity as well as the vertical sidewall of the developed resist pattern, which was used as a core-mandrel. In aerial image optimization, mask CD, mask pitch, target CD, defocus, and illumination settings were identified as influential factors in the CD uniformity. An over-exposure from a large mask CD was discovered to be beneficial to the CD maintenance as was a vertical sidewall of the resist pattern, although the CD uniformity across the focus reversely deteriorates with an increase in the ILS. As for wafer-level CD uniformity control, ASML's Spacer Controller was able to correct CD nonuniformity of post-etch patterns across the intra-and inter-fields of the wafer by adjusting the local dose during the lithographic exposure.