Wafer Level Reliability Characterization of 2.5D IC packages

Jayabalan, J.; Chinq, Jong Ming; Chidambaram, Vivek; Siang, Sharon Lim Pei; Ming, Calvin Chua Hung; Bhattacharya, Shuvajit

doi:10.1109/eptc.2018.8654428

Cited by 3 publications

(3 citation statements)

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“…28 test points were measured for functionality monitoring, which includes Ohmic continuity and diode continuity. 1-4 daisy chain represents Ohmic continuity and 5-28 daisy chain indicates diode continuity [5]. No any significant variation in the electrical results was observed (Fig.…”

Section: Reliability Evaluationmentioning

confidence: 92%

“…Furthermore, active Si interposer (ATSI) concept is introduced, which enhances signal integrity, power integrity, lower power consumption and cost-effectiveness. This is achieved by integrating the passive device and the active circuits on the same Si interposer [3]- [5]. The ATSI is fabricated in 130nm CMOS, which provides/supports ADC, DAC, PMU, I/O, analog and ESD functions with Via-last TSV.…”

Section: Introductionmentioning

confidence: 99%

“…The concept of stacking and integrating different tech nodes chips heterogenously, which includes I/O chips and FPGA using ATSI is demonstrated. TSV technology is incorporated in the ATSI for better electrical connection with minimum propagation time delay, lower power consumption and smaller foot factors [3]- [5]. Different temporary bonding materials and debonding methods were evaluated for handling 40µm thin ATSI.…”

Section: Introductionmentioning

confidence: 99%

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Heterogeneous System Level Integration Using Active Si Interposer

Chidambaram

Siang

Wang

et al. 2019

IEEE J. Electron Devices Soc.

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Achieved system level heterogeneous integration involving 130 nm tech node active Si interposer, two 65 nm tech node I/O chips and one 28 nm tech node FPGA die. Chip on Chip on Substrate packaging methodology was demonstrated for handling active Si interposer die as thin as 40 µm. Different packaging approaches were evaluated and the results are benchmarked. In addition, active Si interposer concept is introduced to provide Analog to Digital Converter (ADC), Digital to Analog Converter (DAC) and Power Management Unit (PMU) functions to support high-performance logic. Furthermore, benefits of active Si approach such as system scaling and cost-effectiveness have been demonstrated. "Via Last" TSV approach is used for the fabrication of 130 nm tech node active Si interposer. It was confirmed that appropriate selection of temporary bonding material plays a critical role in device wafer warpages in via last TSV process flow. Functionality checks were carried out on all samples subjected to pre-and post-reliability assessments, which include thermal cycling (TC), moisture sensitivity tests (MSL) and highly accelerated stress tests (HAST). All samples were found to be functional with no deterioration in performance despite being subjected to reliability tests and high-voltage stress tests.

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Section: Reliability Evaluationmentioning

confidence: 92%

Section: Introductionmentioning

confidence: 99%