Wafer sampling by regression for systematic wafer variation detection

A Literature Review on Sampling Techniques in Semiconductor Manufacturing

“…A Sample Planner is developed by KLATencor to assist in the development of cost-effective defect inspection sampling strategies, and to provide an accurate assessment of whether monitor reduction and/or elimination should be pursued for cost savings. The results of the project indicate that the costs due to defect excursions could com- [33] 1995 * * Kuo et al [34] 1996 * * * Kuo et al [12] 1997 * * Babikian and Engelhard [35] 1998 * Williams et al [36] 1999 * * Williams et al [37] 1999 * * Langford et al [38] 2000 * * Nurani and Shantikumar [39] 2000 * * * Lee et al [40] 2001 * * Wootton et al [41] 2001 * * Allebé et al [42] 2002 * * Lee [43] 2002 * * Song-Bor et al [44] 2003 * * Sullivan et al [45] 2004 * * Moon et al [46] 2005 * * Boussetta and Cross [14] 2005 * * Mouli [13] 2005 * Shantikumar [47] 2007 * Mouli et al [48] 2007 * * Bunday et al [49] 2008 * Veetil et al [50] 2009 * * Chen et al [51] 2009 * * Sahnoun et al [52] 2010 * * Sahnoun et al [53] 2010 * * * Good et al [54] 2010 * * Nduhura Munga et al [55] 2011 * * pletely eradicate any projected savings from monitor reduction activities, due to the additional defect excursions that would be missed by the reduced inspection sampling plan. Wootton et al [41] present a study performed between KLA-Tencor and Motorola.…”