Wafer-scale Fabrication of CMOS-compatible Trapping-mode Infrared Imagers with Colloidal Quantum Dots

Abstract

Silicon-based complementary metal-oxide-semiconductors (CMOS) devices have dominated the technological revolution in the past decades. With increasing demands in machine vision, autonomous driving, and artificial intelligence, Si-CMOS imagers, as the major optical information input devices, face great challenges in spectral sensing ranges. In this paper, we demonstrate the development of CMOS-compatible infrared colloidal quantum dots (CQDs) imagers in the broadband short-wave and mid-wave infrared ranges (SWIR and MWIR, 1.5-5µm). A new device architecture of trapping-mode detector is proposed, fabricated, and demonstrated with lowered dark currents and improved responsivity. The CMOS-compatible fabrication process is completed with two-step sequential spin-coating processes of intrinsic and doped HgTe CQDs on an 8-inch CMOS readout wafer with photoresponse non-uniformity (PRNU) down to 4%, dead pixel rate of 0%, external quantum efficiency up to 175%, and detectivity as high as 2×1011Jones for extended SWIR (cut-off wavelength=2.5µm) @ 300K and 8×1010Jones for MWIR (cut-off wavelength=5.5µm) @ 80K. Both SWIR images and MWIR thermal images are demonstrated with great potential for semiconductor inspection, chemical identification, and temperature monitoring.

Mapping the Energy Landscape from a Nanocrystal-Based Field Effect Transistor under Operation Using Nanobeam Photoemission Spectroscopy

“…For illustration, scanning soft X-ray photoemission microscopy is applied to a HgTe NC-based FET; see Figures and S1–S4. Among existing NCs, HgTe NCs appear particularly suited for infrared optoelectronics, as shown in a wide range of devices: infrared cameras, , spectrometers, , phototransistors, − (multicolor) photodiodes, − and light emitting devices.,, Because photoemission is a surface-sensitive method, it appears to be better suited for investigating devices with the active layer on top. To overcome this limitation and take advantage of the spatial resolution of the setup, we focus here on a planar transistor for its laterally accessible interfaces.…”