Wafer-Scale Si–GaN Monolithic Integrated E-Mode Cascode FET Realized by Transfer Printing and Self-Aligned Etching Technology

Zhang, Jiaqi; Zhang, Weihang; Wu, Yichang; Zhang, Yachao; Peng, Yue; Feng, Zhaoqing; Zhao, Shenglei; Zhang, Chunfu

doi:10.1109/ted.2020.3001083

Cited by 18 publications

(19 citation statements)

References 18 publications

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“…After that, PR (photoresist) anchors were formed by photolithography, as shown in Figure 1(aiv). These PR anchors are a photoresist pattern formed by lithographic, and it can prevent the Si mesas from scattering or moving when the BOX is completely removed by HF [7,8,17]. The substrates obtained through the above process are shown in Figure 1b.…”

Section: Experiments Processmentioning

confidence: 99%

“…Therefore, it is extremely urgent to integrate monocrystalline silicon devices and compound semiconductor devices through heterogeneous integration to meet the development requirements of ultra-miniaturization, intelligence, and diversification of electronic systems, and to break through the limitations of silicon bulk materials. There are several methods in the current stage of heterogeneous integration technology, such as epitaxial growth, bonding, three-dimensional packaging, and transfer printing [2][3][4][5][6][7][8][9]. This article mainly studies the transfer technology applied in the field of heterogeneous integration.…”

Section: Introductionmentioning

confidence: 99%

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Optimization of Sacrificial Layer Etching in Single-Crystal Silicon Nano-Films Transfer Printing for Heterogeneous Integration Application

Zhang

Yang

et al. 2021

Nanomaterials

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As one of the important technologies in the field of heterogeneous integration, transfer technology has broad application prospects and unique technical advantages. This transfer technology includes the wet chemical etching of a sacrificial layer, such that silicon nano-film devices are released from the donor substrate and can be transferred. However, in the process of wet etching the SiO2 sacrificial layer present underneath the single-crystal silicon nano-film by using the transfer technology, the etching is often incomplete, which seriously affects the efficiency and quality of the transfer and makes the device preparation impossible. This article analyzes the principle of incomplete etching, and compares the four factors that affect the etching process, including the size of Si nano-film on top of the sacrificial layer, the location of the anchor point, the shape of Si nano-film on top of the sacrificial layer, and the thickness of the sacrificial layer. Finally, the etching conditions are obtained to avoid the phenomenon of incomplete etching of the sacrificial layer, so that the transfer technology can be better applied in the field of heterogeneous integration. Additionally, Si MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) on sapphire substrate were fabricated by using the optimized transfer technology.

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Section: Experiments Processmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Optimization of Sacrificial Layer Etching in Single-Crystal Silicon Nano-Films Transfer Printing for Heterogeneous Integration Application

Zhang

Yang

et al. 2021

Nanomaterials

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“…In recent years, there have been many reports on the fabrication of various monolithic heterogeneous integrated devices and circuits by different heterogeneous integration methods, heteroepitaxy [1]- [3], wafer bonding [4], [5] and transfer printing [6], [5]- [8], respectively. At present, monolithic heterogeneous integrated devices reported include Cascode FETs, Cascode diodes, flexible UV PDs and UV LEDs, etc [1], [2], [5], [6], [8]- [12]. And monolithic heterogeneous integrated circuits reported include GaN-Si hybrid amplifier, current mirror integrated circuits and half-bridge circuits [13].…”

Section: Introductionmentioning

confidence: 99%

Enhanced breakdown voltage of Si-GaN monolithic heterogeneous integrated Cascode FETs by the device structure design

Zhang

Wan

et al. 2022

Solid-State Electronics

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“…But the difficulty to realize enhanced-mode (E-mode) operation has become one of the key factors which limit their large-scale commercialization [3]. At present, the main solutions include recess gate structure [4], fluoride plasma treatment [5], p-type GaN (p-GaN) gate [6][7][8][9][10], and Cascode structure [11]. Among them, only the p-GaN gate has been proved as a promising strategy in practical application.…”

Section: Introductionmentioning

confidence: 99%

Wide-range-adjusted threshold voltages for E-mode AlGaN/GaN HEMT with a p-SnO cap gate

et al. 2021

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p-GaN cap layer has been recognized as a commercial technology to manufacture enhanced-mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMT); however, the difficult activation of Mg doping and etching damage of p-GaN limit the further improvement of device performance. Thus, the more cost-effective cap layer has attracted wide attention in GaN-based HEMT. In this paper, p-type tin monoxide (p-SnO) was firstly investigated as a gate cap to realize E-mode AlGaN/GaN HEMT by both Silvaco simulation and experiment. Simulation results show that by simply adjusting the thickness (50 to 200 nm) or the doping concentration (3 × 10 17 to 3 × 10 18 cm −3 ) of p-SnO, the threshold voltage (V th ) of HEMT can be continuously adjusted in the range from zero to 10 V. Simultaneously, the device demonstrated a drain current density above 120 mA mm −1 , a gate breakdown voltage (V BG ) of 7.5 V and a device breakdown voltage (V B ) of 2470 V. What is more, the etching-free AlGaN/ GaN HEMT with sputtered p-SnO gate cap were fabricated, and achieved a positive V th of 1 V, V BG of 4.2 V and V B of 420 V, which confirms the application potential of the p-SnO film as a gate cap layer for E-mode GaN-based HEMT. This work is instructive to the design and manufacture of p-oxide gate cap E-mode AlGaN/GaN HEMT with low cost.

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Wafer-Scale Si–GaN Monolithic Integrated E-Mode Cascode FET Realized by Transfer Printing and Self-Aligned Etching Technology

Cited by 18 publications

References 18 publications

Optimization of Sacrificial Layer Etching in Single-Crystal Silicon Nano-Films Transfer Printing for Heterogeneous Integration Application

Optimization of Sacrificial Layer Etching in Single-Crystal Silicon Nano-Films Transfer Printing for Heterogeneous Integration Application

Enhanced breakdown voltage of Si-GaN monolithic heterogeneous integrated Cascode FETs by the device structure design

Wide-range-adjusted threshold voltages for E-mode AlGaN/GaN HEMT with a p-SnO cap gate

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