Wafer-shape based in-plane distortion predictions using Superfast 4G metrology

Dijk, Leon van; Mileham, Jeffrey; Malakhovsky, Ilja; Laidler, David; Dekkers, Harold; Elshocht, Sven Van; Anberg, Doug; Owen, David M.; Haren, Richard van

doi:10.1117/12.2257475

Cited by 10 publications

(10 citation statements)

References 2 publications

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“…Although a wafer scaling difference of -0.28 ppm was observed, this was not reflected in the wafer edge performance. The -0.28-ppm delta as measured on the bottom wafer suggests that the bonding step introduces a tensile stress which should manifest itself in a curl-up of the wafer edge beyond the last burl [7]. The distortion vectors in this region should point towards the wafer center.…”

Section: Bulk Simentioning

confidence: 99%

Enabling layer transfer and back-side power delivery network applications by wafer bonding and scanner correction optimizations

Haren

Minghetti

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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Apart from the ever-continuing lateral scaling in the xy-plane to increase the transistor density, additional new concepts find their way to the semiconductor industry too. These concepts are based on making more use of the third dimension. One relatively simple idea would be to create a second layer of transistors to double the transistor density. However, the material requirements are high and the quality of the layer deposition by conventional Chemical Vapor Deposition (CVD) techniques is insufficient. Another application to free up real estate, enabling a smaller cell size and hence an increased transistor density, is to power-up the transistors from the backside. The power rails for logic devices are historically defined in the first Metal layer and consume quite some space. Bringing the power rails to the backside will free up space. However, access to the transistor layer from the backside of the wafer is far from trivial due to the presence of a 775-μm thick silicon substrate. The answer to the challenges mentioned above is wafer-to-wafer direct bonding. Although this technique is not new and already widely used in the semiconductor industry to manufacture CMOS Image Sensors (CIS), it currently finds its way to the high-end logic markets. In case of layer transfer, a crystalline silicon layer is created by bonding a Silicon-On- Insulator (SOI) wafer to the already existing device wafer. After the bonding step, the substrate of the SOI wafer will be removed leaving the crystalline silicon layer behind. Access to the transistor layer from the wafer backside can be enabled by wafer-to-wafer bonding as well. To this end, a completed device wafer will be bonded to an (un-patterned) carrier wafer. The substrate of the original device wafer will be removed, enabling access from the backside. Wafer-towafer bonding applications can only be enabled in case the induced wafer deformations are low or when they can easily be corrected during the subsequent exposures on the scanner. At CEA-Leti, a dedicated test vehicle process flow has been developed to characterize the wafer bonding-induced distortion fingerprints for both the layer transfer and the backside power delivery network applications. The wafer process flow has been simplified without losing the industry relevant on-product overlay challenges. Wafers have been created to enable an extremely dense characterization of the wafer bonding induced fingerprint. The methodology we applied enables us to isolate the wafer bonding induced distortion fingerprint, something that is difficult to do in a production environment. The Back-Side Power Delivery Network (BS-PDN) application is the most challenging one. The initial raw measured wafer distortion fingerprints are around 60 to 80-nm. These numbers can already be easily brought down by scanner corrections to ~15-nm (mean+3σ) without too much effort. However, these numbers are too large for the 2-nm technology node and beyond, and further improvement is required. The goal of this paper is to present the path forward t...

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Section: Bulk Simentioning

confidence: 99%

Enabling layer transfer and back-side power delivery network applications by wafer bonding and scanner correction optimizations

Haren

Minghetti

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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“…The difference in target length scale may contribute to additional discrepancy. Thirdly, while the distortion measurement is derived from a freestanding wafer shape, overlay is measured on a chucked surface, which may distort the wafer unevenly [5]. Lastly, the post-bond wafer still consists of the device and handler substrate, whereas the device substrate is removed prior to the scanner measurements.…”

Section: Relationship Between Post-bond Distortion and Overlaymentioning

confidence: 99%

Overlay performance in permanent bonded wafer integration schemes

Belyansky

Netzband

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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Several next generation integration schemes – e.g. for 3D stacked transistors, backside power distribution, and advanced packaging involve permanent wafer bonding steps and drive to sub-10nm overlay requirements post bonding. Distortion during wafer bonding is a major determinant of best achievable overlay between post to pre bonding lithography layers. Here, we investigate correlations between wafer bonding process and post bonding overlay performance through a combination of experiment and modelling. We use a custom test vehicle to collect wafer distortion data from pre- and post-bond processes, as well as overlay data after the post-bond processing steps (anneal and thin). The results establish direct relationships between incoming wafer distortion, bonder-induced distortion and post-bond lithography overlay to a pre-bond level. We also use the experimental results to validate a wafer bonding simulation model to further physical explanation of process-induced distortion. The experiment results will enable advanced wafer bonding process controls to optimize distortion and scanner overlay to meet technology targets. The results will also help guide hardware design to improve distortion fingerprints to best improve scanner overlay, as well as address the distortion challenges from incoming wafers.

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“…In this paper, we will study three wafers that have been used to validate wafer-shape based IPD predictions in earlier work 1,3 . The three wafers are bare silicon wafers with many alignment marks etched into the silicon with a well-defined etch depth.…”

Section: The Wafers Used For Testingmentioning

confidence: 99%

“…It is important to realize, though, that the latter is only beneficial when the distortions vary significantly from wafer-to-wafer and/or lot-to-lot, because otherwise an overlay feedback solution may already be sufficient, provided that dense intra-die (in device) measurements are available. Moreover, wafer alignment marks are still required to anchor the IPD map and/or correct for scanner-induced distortions 3 .…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, a stringent requirement for successful implementation of free-form wafer-shape based distortion predictions is that the shape measurements are sufficiently accurate. ASML has demonstrated in earlier work that in-plane distortions due to front-side thin film stress can be predicted from free-form wafer-shape measurements using a Finite Element based prediction model within an accuracy of 1 nm or less 1,3 . The same model will be used to predict the in-plane distortions and we will validate whether they are in agreement with the process-induced distortions as measurement on the scanner.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

New technique for measuring free-form wafer shape for feed-forward overlay corrections

Kurteva,

Castro Luis,

Trujillo-Sevilla

et al. 2023

International Conference on Extreme Ultraviolet Lithography 2023

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Wafer-shape based in-plane distortion predictions using Superfast 4G metrology

Cited by 10 publications

References 2 publications

Enabling layer transfer and back-side power delivery network applications by wafer bonding and scanner correction optimizations

Enabling layer transfer and back-side power delivery network applications by wafer bonding and scanner correction optimizations

Overlay performance in permanent bonded wafer integration schemes

New technique for measuring free-form wafer shape for feed-forward overlay corrections

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