Wafer warpage analysis of stacked wafers for 3D integration

Argon plasma treatment on Cu surface for Cu bonding in 3D integration and their characteristics

“…These may be due to a too rough surface with plasma treatment and Cu oxidation before and during a thermo-compression bonding process. Many studies on Cu-to-Cu thermo-compression bonding have been reported [4][5][6][7][8], but most of Cu bonding processes were at the high temperature above 350 • C. Cu-to-Cu bonding even at 350 • C was not well bonded and had a seam at the bonded interface. Park et al was studied a wet chemical pre-treatment to improve Cu-to-Cu bonding quality at 350 • C bonding process [22].…”

“…Among various bonding methods Cu-to-Cu metallic bonding is a key process that needs to be developed, especially for its high density and performance. Many studies on the Cu-to-Cu bonding process have been reported so far [4][5][6][7][8]22]. The advantages of Cu as a bonding material are its mainstream CMOS material, low resistivity, high thermal conductivity, good resistance to electromigration (EM), and no brittle intermetallic compound (IMC) formation.…”

A New Approach for the Control and Reduction of Warpage and Residual Stresses in Bonded Wafer

“…The residual stress in the die influences the manufacturing quality in the following process steps, mostly because the system experiences different thermal load; finally, the performance of the device is also affected [ 12 , 13 ]. Moreover, by advancing the complexity of MEMS structures and exploiting 3D integration, the residual stress due to bonding affects the warpage of the overall stack [ 14 ]. There are several methods to measure the wafer curvature: the main ones exploit optical methods, but other approaches has been followed, see Chapter 14 in [ 15 ] or e.g., [ 16 , 17 ].…”

“…This thermal gradient approach results in a significant warpage reduction for silicon to glass wafer bonding. The layer thickness has been recognized as important also in [ 14 ], and particularly when more than two wafers are stacked; while the warping increases with the stack, the increment of wafer curvature reduces as the number of stack increases. In order to reduce the residual stress effect, appropriate material choice has been suggested, e.g., for temporary bonding materials within the carrier wafer [ 21 ].…”

Manufacturing yield challenges for wafer-to-wafer integration

“…특히 3D integration 기술은 메 모리(memory) 소자의 밀도(density)와 대역폭(bandwidth) 이 높아지고, 로직(logic) 소자의 속력(Speed)과 전력 (power)이 급상승하는 기술 추세에 맞추어, 차세대 고성 능화 소형화의 핵심기술로서 그동안 많은 연구가 진행되 어 왔다. [1][2][3][4][5][6][7][8][9] 3D integration 기술 중 wafer-to-wafer(W2W)…”