2012 14th International Conference on Electronic Materials and Packaging (EMAP) 2012
DOI: 10.1109/emap.2012.6507849
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Warpage, stresses and KOZ of 3D TSV DRAM package during manufacturing processes

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Cited by 4 publications
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“…In the progress of semiconductor design methodologies [1][2][3][4][5], more and more integrated circuit components can be patterned then etched onto semiconductor wafers. This is true especially in the DRAM (dynamic random access memory) industry, where, in addition to the demands of increasing the speeds of access and longer lifespans, there are other demands to be met: for example, each successive generation of the DRAM chips must become smaller and more compact, so that more memory can be fit into an even smaller space.…”
Section: Introductionmentioning
confidence: 99%
“…In the progress of semiconductor design methodologies [1][2][3][4][5], more and more integrated circuit components can be patterned then etched onto semiconductor wafers. This is true especially in the DRAM (dynamic random access memory) industry, where, in addition to the demands of increasing the speeds of access and longer lifespans, there are other demands to be met: for example, each successive generation of the DRAM chips must become smaller and more compact, so that more memory can be fit into an even smaller space.…”
Section: Introductionmentioning
confidence: 99%