WCET-Aware Dynamic I-Cache Locking for a Single Task

Abstract

Caches are widely used in embedded systems to bridge the increasing speed gap between processors and off-chip memory. However, caches make it significantly harder to compute the worst-case execution time (WCET) of a task. To alleviate this problem, cache locking has been proposed. We investigate the WCETaware I-cache locking problem and propose a novel dynamic I-cache locking heuristic approach for reducing the WCET of a task. For a nonnested loop, our approach aims at selecting a minimum set of memory blocks of the loop as locked cache contents by using the min-cut algorithm. For a loop nest, our approach not only aims at selecting a minimum set of memory blocks of the loop nest as locked cache contents but also finds a good loading point for each selected memory block. We propose two algorithms for finding a good loading point for each selected memory block, a polynomial-time heuristic algorithm and an integer linear programming (ILP)-based algorithm, further reducing the WCET of each loop nest. We have implemented our approach and compared it to two state-of-the-art I-cache locking approaches by using a set of benchmarks from the MRTC benchmark suite. The experimental results show that the polynomial-time heuristic algorithm for finding a good loading point for each selected memory block performs almost equally as well as the ILP-based algorithm. Compared to the partial locking approach proposed in Ding et al. [2012], our approach using the heuristic algorithm achieves the average improvements of 33%, 15%, 9%, 3%, 8%, and 11% for the 256B, 512B, 1KB, 4KB, 8KB, and 16KB caches, respectively. Compared to the dynamic locking approach proposed in Puaut [2006], it achieves the average improvements of 9%,

Reducing the WCET and analysis time of systems with simple lockable instruction caches

“…In order to perform a simple WCET calculation, let us just account for hits and misses considering that each loaded cache line is equivalent to a miss (M i ). For the loading and locking points, a function call (with its corresponding executed instructions and cache misses) is assumed [22]. So, for our proposal to be in disadvantage, let us consider that the cost of each loading point is just that of a single miss (M p ).…”

“…Nevertheless, it is important to remember that the heuristics of the proposal in Fig 2A requires a partial set-level locking cache, whereas ours assumes just a fully-lockable cache. Since the hardware is completely different, this means that our methods are not comparable, except when the whole cache is locked, as in Fig 2. Also, note that other approaches must perform preliminary or convergent WCET analyses in order to set their loading points, which imply much longer analysis times [19,22].…”

“…We consider an instruction cache hit cost of 1 cycle, and a relatively low memory latency (10 cycles). Other studies consider off-chip main memories and assume a higher miss penalty, such as 30 cycles [22]. Clearly, improvement in such systems would be much higher.…”

“…Finally, some studies assume partial set-level lockable caches. For each cache set, these caches are able to track a variable number of non-locked lines sorted in LRU order, and lock the remaining ones [21,22]. Control complexity and storage to support this fine-grained locking-replacement surpasses the abilities of conventional caches and, of course, that of fully-lockable caches.…”

“…The high number of configurations supported by partial set-level lockable caches requires high analysis times. For instance, a convergence process consisting of two steps has been proposed [22]. The first step performs a WCET analysis assuming a conventional instruction cache which may have some locked lines.…”