WCET-driven cache-aware code positioning

Falk, Heiko; Kotthaus, Helena

doi:10.1145/2038698.2038722

Cited by 16 publications

(9 citation statements)

References 18 publications

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“…Similar techniques can be applied in software [3,14,15,16,17] or in hardware [18,19,20] with different granularities. Software partitioning techniques usually rely on an indirect control over the cache, manipulating address-to-line mapping at OS, compiler, or application level.…”

Section: B Cache Managementmentioning

confidence: 99%

“…Moreover, similarly to what we did on the P4080 platform, the proposed technique can be applied to a variety of platforms currently available on the market. Finally, unlike many works that have been presented in the past, our technique works on both data and code regions [3,4,5]. Experimental results show that, in the considered benchmarks, eliminating the interference in the last level cache can lead up to a 250% improvement of the execution time, with a resulting cache occupation as small as 4 memory pages.…”

Section: Introductionmentioning

confidence: 96%

See 1 more Smart Citation

Real-time cache management framework for multi-core architectures

Mancuso

Dudko

Betti

et al. 2013

2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

147

111

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Abstract-Multi-core architectures are shaking the fundamental assumption that in real-time systems the WCET, used to analyze the schedulability of the complete system, is calculated on individual tasks. This is not even true in an approximate sense in a modern multi-core chip, due to interference caused by hardware resource sharing. In this work we propose (1) a complete framework to analyze and profile task memory access patterns and (2) a novel kernel-level cache management technique to enforce an efficient and deterministic cache allocation of the most frequently accessed memory areas. In this way, we provide a powerful tool to address one of the main sources of interference in a system where the last level of cache is shared among two or more CPUs. The technique has been implemented on commercial hardware and our evaluations show that it can be used to significantly improve the predictability of a given set of critical tasks.

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Section: B Cache Managementmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 96%

Real-time cache management framework for multi-core architectures

Mancuso

Dudko

Betti

et al. 2013

2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

147

111

View full text Add to dashboard Cite

show abstract

“…WCC's code positioning [Falk and Kotthaus 2011] aims to systematically reduce I-cache conflict misses and thus to reduce the WCET of a program. It uses a cache conflict graph (CG) as the underlying model of a cache's behavior.…”

Section: Examples Of Wcet-aware Optimizationsmentioning

confidence: 99%

Building timing predictable embedded systems

Axer

Ernst

Falk³

et al. 2014

ACM Trans. Embed. Comput. Syst.

Self Cite

101

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A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performanceenhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large degree of uncertainty and make guarantees harder to provide. The intention of this article is to summarize the current state of the art in research concerning how to build predictable yet performant systems. We suggest precise definitions for the concept of "predictability", and present predictability concerns at different abstraction levels in embedded system design. First, we consider timing predictability of processor instruction sets. Thereafter, we consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach using the synchronous programming paradigm, as well as an environment that provides timing semantics for a mainstream programming language (in this case C). We present techniques for achieving timing predictability on multicores. Finally, we discuss how to handle predictability at the level of networked embedded systems where randomly occurring errors must be considered.

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“…They placed procedures on the worst-case path that call each other frequently close together to reduce conflicts. Falk et al [15] recently used block and procedure positioning based on cache conflict graphs to reduce the WCET estimate. Unlike previous work, they accounted for the cache configuration including the associativity, size and replacement policy.…”

Section: Related Workmentioning

confidence: 99%

Optimising task layout to increase schedulability via reduced cache related pre-emption delays

Lunniss

Altmeyer

Davis

2012

Proceedings of the 20th International Conference on Real-Time and Network Systems

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Cache memories have been introduced into embedded systems to prevent memory access times from becoming an unacceptable performance bottleneck. For hard real-time systems, it is vital that an accurate estimate of the worst-case response time for each task can be determined. Memory and cache are split into blocks containing instructions and data. During a pre-emption, blocks from the pre-empting task can evict those of the pre-empted task. When the pre-empted task is resumed, if it then has to re-load the evicited blocks, cache related pre-emption delays (CRPD) are introduced which then affect the worst-case response times of the task. Because the position of code in memory determines where the code will be placed in cache, different layouts result in different CRPD and worst-case response times for tasks. We introduce an approach that uses simulated annealing to find layouts that minimise the CRPD incurred due to a pre-emption. This in turn reduces the worst-case response times of tasks, which increases the schedulability of the taskset. We use schedulability analysis that captures whether a block will have to be re-loaded after a pre-emption, to drive the algorithm towards a near optimal solution. After explaining our approach, we present a number of experiments which demonstrate its effectiveness for a number of different system, task and cache configurations.

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WCET-driven cache-aware code positioning

Cited by 16 publications

References 18 publications

Real-time cache management framework for multi-core architectures

Real-time cache management framework for multi-core architectures

Building timing predictable embedded systems

Optimising task layout to increase schedulability via reduced cache related pre-emption delays

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