WCET estimation for executables in the presence of data caches

Sen, Rathijit; Srikant, Y. N.

doi:10.1145/1289927.1289960

Cited by 41 publications

(46 citation statements)

References 11 publications

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“…This does not however capture array access patterns. Sen and Srikant (2007) presented an approach that combines automatic executable analysis to determine the addresses accessed and a Must analysis for determining cache behaviour, both using Abstract Interpretation. The overall problem is divided into four sub-problems: address analysis, cache analysis, access sequencing, and worst-case path analysis.…”

Section: Discussionmentioning

confidence: 99%

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Response-time analysis for fixed-priority systems with a write-back cache

2018

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This paper introduces analyses of write-back caches integrated into response-time analysis for fixed-priority preemptive and non-preemptive scheduling. For each scheduling paradigm, we derive four different approaches to computing the additional costs incurred due to write backs. We show the dominance relationships between these different approaches and note how they can be combined to form a single state-of-the-art approach in each case. The evaluation explores the relative performance of the different methods using a set of benchmarks, as well as making comparisons with no cache and a write-through cache. We also explore the effect of write buffers used to hide the latency of write-through caches. We show that depending upon the depth of the buffer used and the policies employed, such buffers can result in domino effects. Our evaluation shows that even ignoring domino effects, a substantial write buffer is needed to match the guaranteed performance of write-back caches.

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Section: Discussionmentioning

confidence: 99%

“…The latter is solved using an ILP formulation. Sen and Srikant (2007) use Circular Linear Progressions (CLPs) to provide a strided linear approximation of the discrete set of memory addresses that may be accessed by a particular instruction.…”

Section: Discussionmentioning

confidence: 99%

Response-time analysis for fixed-priority systems with a write-back cache

2018

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“…[2], [3], [4], [5], takes the two-step approach already explained in Section II: First, an address analysis, e.g. an interval analysis, computes an approximation to the set of possibly accessed addresses for each memory reference.…”

Section: Related Workmentioning

confidence: 99%

“…They compute may-cache, dominator and post-dominator information in order to classify the memory references. Sen et al [3] propose Circular Linear Progressions (CLPs) for address analysis. Those are more expressive than intervals and allow to precisely model memory references that depend on loop induction variables.…”

Section: Related Workmentioning

confidence: 99%

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Relational Cache Analysis for Static Timing Analysis

Hahn

Grund

2012

2012 24th Euromicro Conference on Real-Time Systems

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Abstract-Static cache analysis is an indispensable part of static timing analysis, which is employed to verify the timing behaviour of programs in safety-critical real-time systems.State-of-the-art cache analyses classify memory references as 'always hit', 'always miss', or 'unknown'. To do so, they rely on a preceding address analysis that tries to determine the referenced addresses. If a referenced address is not determined precisely, however, those cache analyses cannot predict this reference as hit or miss. On top of that, information about other cache contents is lost upon such references.We present a novel approach to static cache analysis that alleviates the dependency on precise address analysis. Instead of having to argue about concrete addresses, we only need to argue about relations between referenced addresses, e.g. 'accesses same memory block' or 'maps to different cache set'. Such relations can be determined by congruence analyses, without precise knowledge about the actual addresses. The subsequent cache analysis then only relies on relations to infer cache information and to classify references.One advantage of this approach is that hits can be predicted for references with imprecisely determined addresses; even if there is no information about accessed addresses. In particular, this enables the prediction of hits for references whose addresses depend on an unknown stack pointer or even depend on the program input. Relational cache analysis is always at least as precise as the corresponding state-of-theart cache analysis. Furthermore, we demonstrate significant improvements for three classes of program constructs.

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2013

Time‐Predictable Architectures

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WCET estimation for executables in the presence of data caches

Cited by 41 publications

References 11 publications

Response-time analysis for fixed-priority systems with a write-back cache

Response-time analysis for fixed-priority systems with a write-back cache

Relational Cache Analysis for Static Timing Analysis

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