2004
DOI: 10.1109/tvlsi.2004.837985
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Weighted pseudorandom hybrid BIST

Abstract: Abstract-This paper presents a new test data-compression scheme that is a hybrid approach between external testing and built-in self-test (BIST). The proposed approach is based on weighted pseudorandom testing and uses a novel approach for compressing and storing the weight sets. Three levels of compression are used to greatly reduce test costs. Experimental results show that the proposed scheme reduces tester storage requirements and tester bandwidth requirements by orders of magnitude compared to conventiona… Show more

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Cited by 50 publications
(20 citation statements)
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“…[6]. Most recently, new techniques were proposed by Jas, Krishna and Touba [4] to compress and store weight sets, which can reduce tester storage requirements and tester bandwidth requirements by orders of magnitude. However, most biased random testing methods need to store multiple weight sets on-chip, and multiple session testing is usually necessary, which can make the control logic very complex.…”
Section: Introductionmentioning
confidence: 99%
“…[6]. Most recently, new techniques were proposed by Jas, Krishna and Touba [4] to compress and store weight sets, which can reduce tester storage requirements and tester bandwidth requirements by orders of magnitude. However, most biased random testing methods need to store multiple weight sets on-chip, and multiple session testing is usually necessary, which can make the control logic very complex.…”
Section: Introductionmentioning
confidence: 99%
“…In Table 2, we compare the proposed method with the weighted pseudo-random hybrid BIST method [8]. Since we use a single scan chain in our experiments (note that compression ratio achieved by the proposed method is independent of the number of scan chains), results for [8] are shown for the lowest (8) scan chain versions of benchmark circuits published in that paper.…”
Section: Resultsmentioning
confidence: 99%
“…Unlike [13] where weight sets are stored in a RAM, in [21,22], weight sets are hardwired into random logic (decoder) to minimize hardware overhead. Recently, an application of weighted random pattern testing techniques to test data compression was presented in [8,11,12], where weight data of the inputs that have signal probability other than 0.5 are stored in an on-chip memory and accessed to generate weighted random patterns during test application. Test data for inputs that have 0.5 signal probability are generated by an on-chip random pattern generator.…”
Section: Introductionmentioning
confidence: 99%
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