Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip

Jafari, Fahimeh; Jantsch, Axel; Lu, Zhonghai

doi:10.1109/tvlsi.2016.2556007

Cited by 10 publications

(5 citation statements)

References 43 publications

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“…Anyhow the area and power utilization are very much elevated. A weighted round robin arbiter is built by using a generic algorithm-based optimization method [21]. Each and every input port is having a suitable weight.…”

Section: Related Workmentioning

confidence: 99%

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Singh

Ravindra²,

Naik

2022

IJIE

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Network-on-chip (NoC) provides solution to overcome the complications of the on-chip interconnect architecture in multi-core systems. It mainly consists of router, links and network interface. An essential component of on-chip router is an arbiter that significantly impacts the performance of the router. The arbiter should provide fast and fair arbitration when it is placed in Critical Path Delay (CPD) systems. The main aim of this research work is to design a novel arbiter for an effective network scheduler in complex real time applications. At the same time resource allocation and power consumption should be very low. Previously, a novel gate level Ping Lock Arbiter (PLA) is designed to overcome the limited fair arbitration in Improved Ping Pong Arbiter (IPPA) with less delay. But the chip size and power consumption are very high. To overcome this problem, an Effective Gate Diffusion Input (EGDI) logic-based CMOS scheme is used to design a novel Compact Ping Lock Arbiter (CPLA). The proposed CPLA is compared with the existing PLA based on static CMOS scheme. The comparison between the conventional and proposed arbiter is carried out to analyze the area, delay and power by using Tanner Tool 14.1 with 250nm and 45nm technology. The proposed CPLA is suitable for compact and smart applications with glitch free and fair arbitration. The proposed CPLA presents 41.2% reduction in total area consumption. It also provides 47.12% average Area and Power Product (APP) reduction when compared to the existing 4-bit PLA. Similarly, the proposed 8-bit CPLA shows 49.48% average APP product shrinkage when compared to conventional 8-bit PLA. For low power and area constraint applications, the proposed CPLA with EGDI is best in comparison to the static CMOS based ping lock round robin arbiter. Therefore, the results demonstrate that the proposed CPLA achieves low power and consumes less area than the existing ping lock arbiter.

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Section: Related Workmentioning

confidence: 99%

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Singh

Ravindra²,

Naik

2022

IJIE

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“…Notations on the Equation 3 are known as: mi,k = matrix for task i and block k wi = priority value for task i t = current time Ti = last time when the task i was served One improvement in RR is weighted Round Robin (WRR). In general, basic RR assumes that all tasks in the system are equal [27] so they must get equal opportunity. In WRR, several tasks may have higher priority rather than others without pre-empting the lower priority tasks [27].…”

Section: Scheduling Algorithm In Computer Systemmentioning

confidence: 99%

“…In general, basic RR assumes that all tasks in the system are equal [27] so they must get equal opportunity. In WRR, several tasks may have higher priority rather than others without pre-empting the lower priority tasks [27]. The weighting process can be static [28] or dynamic [29].…”

Section: Scheduling Algorithm In Computer Systemmentioning

confidence: 99%

Hybrid Make-to-Stock and Make-to-Order (MTS-MTO)Scheduling Model in Multi-Product Production System

Kusuma

2022

IJIE

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In production process, scheduling isan important role in meeting the orders and reducing the cost. This process becomes more complicated when the factory produces various products. Scheduling model in the production process can be divided into two groups: make-to-stock (MTS) and make-to-order (MTO). General constraint in the MTSmodel is limited production capacity and inventory cost. This work aims to propose hybrid MTS-MTO model that can improve lead time and maintain low inventory. In this work, we propose three hybrid MTS-MTO scheduling models for the multi-product production system. In these models, we modify several scheduling algorithms that are used in computer system, such as shortest remaining time(SRT), shortest processing time(SPT), and Round Robin(RR). These models are hybrid (s, S)-first-come-first served (FCFS)model, hybrid modified (s, Q)-SPT model, and modified (s, Q)-SRT model. This model then is implemented into production simulation. In this simulation process, we compare the proposed models with the existing item-by-item based (s, S)model. Based on the simulation result, these proposed models perform better than the basic MTS model. The hybrid (s, Q)-modified SPTmodel performs as the best model in creating high completion ratio, low lead time, and low inventory ratio. In certain condition, our proposed model performs 344 percent in completion ratio, 19.8 percent in lead time, and 3 percent in inventory ratio compared with the existing model.

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“…A generic algorithm-based optimization is applied in weighted RRA. An appropriate weight is allocated for every input port [10]. The input channel which has the highest weight is granted first.…”

Section: Introductionmentioning

confidence: 99%

Design of matrix, distributive round robin, ping pong and enhanced ping lock arbiter for shared resources systems

Lakshminarayanan Venkatara,

Sumithra,

Purushothaman

et al. 2023

IJEECS

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Arbiter is one of the main core elements in the network scheduler. The significant goal of this work is to design a high-speed and low execution-time arbiter with lock free and fair arbitration scheme. In this work, four types of arbiters such as matrix arbiter (MA), ping pong arbiter (PPA), distributive round-robin arbiter (DRRA) and enhanced ping lock arbiter (EPLA) are designed and analyzed area, delay, and speed of arbiters. MA is worked in square matrix format and matrix transition is performed for effective routing. The DRRA is designed by using a multiplexer and counter. Hence an, effective scheduling is carried out in DRRA. Binary tree format is used in PPA. The PPA provides low chip size and high speed than existing MA and DRRA. The PPA limits fair arbitration during uniformly distributed active request patterns. To overcome this problem, PPA is improved with some lock systems to create an EPLA. A new ping lock arbiter (PLA) leaf and PLA inter structure is proposed at the gate level to reduce the execution delay, improve the speed and achieve fair arbitration over all other existing arbiters. Resource allocation, execution delay, and speed are analyzed using the Xilinx Integrated Software Environment (ISE) tool.

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Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip

Cited by 10 publications

References 43 publications

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Hybrid Make-to-Stock and Make-to-Order (MTS-MTO)Scheduling Model in Multi-Product Production System

Design of matrix, distributive round robin, ping pong and enhanced ping lock arbiter for shared resources systems

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