Weighted target indications spiking neural P systems with inhibitory rules and time schedule

Shen, Yongshun; Qiu, Lisha; Yang, Zhen; Zhao, Yuzhen

doi:10.1007/s41965-024-00148-x

J Membr Comput

2024

DOI: 10.1007/s41965-024-00148-x

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Weighted target indications spiking neural P systems with inhibitory rules and time schedule

Yongshun Shen,

Lisha Qiu,

Zhen Yang

et al.

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New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA

Rangel,

Anides,

Vázquez

et al. 2024

Mathematics

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During the last years, the demand for internet-of-things (IoT) resource-constrained devices has grown exponentially. To address this need, several digital methods have been proposed to improve these devices in terms of area and power consumption. Despite achieving significant results, improvement in these factors is still a challenging task. Recently, an emerging computational area has been seen as a potential solution to improving the performance of conventional binary circuits. In particular, this area uses a method based on spiking neural P systems (SN P) to create arithmetic circuits, such as adders, subtractors, multipliers, and divisors, since these components are vital in many IoT applications. To date, several efforts have been dedicated to decreasing the number of neurons and synapses to create compact circuits. However, processing speed is a persistent issue. In this work, we propose four compact arithmetic circuits with high processing speeds. To evaluate their performance, we designed a neuromorphic processor that is capable of performing four operations using dynamic connectivity. As a consequence, the proposed neuromorphic processor achieves higher processing speeds by maintaining low area consumption in comparison with the existing approaches.

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New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA

Rangel,

Anides,

Vázquez

et al. 2024

Mathematics

View full text Add to dashboard Cite

show abstract

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Weighted target indications spiking neural P systems with inhibitory rules and time schedule

Cited by 1 publication

References 46 publications

New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA

New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA

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