Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems

Abstract

We introduce the notion of two-valued digit (twit) as a binary variable that can assume one of two different integer values. Posibits, or simply bits, in 0 1 and negabits in 1 0 , commonly used in two's-complement representations and ( ) encoding of binary signed digits, are special cases of twits. A weighted bit-set (WBS) encoding, which generalizes the two's-complement encoding by allowing one or more posibits and/or negabits in each radix-2 position, has been shown to unify many efficient implementations of redundant number systems. A collection of equally weighted twits, including ones with noncontiguous values (e.g., 1 1 or 0 2 ), can lead to wider representation range without the added storage and interconnection costs associated with multivalued digit sets. We present weighted twit-set (WTS) encodings as a generalization of WBS encodings, examine key properties of this new class of encodings, and show that any redundant number system (e.g., generalized signed-digit and hybrid-redundant systems), including those that are based on noncontiguous and/or zero-excluded digit sets, is faithfully representable by WTS encoding. We highlight this broad coverage by a tree chart having WTS representations at its root and various useful redundant representations at its many internal nodes and leaves. We further examine how highly optimized conventional components such as standard full/half-adders and compressors may be used for arithmetic on WTS-encoded operands, thus allowing highly efficient and VLSI-friendly circuit implementations. For example, focusing on the WBS-like subclass of WTS encodings, we describe a twit-based implementation of a particular stored-transfer representation which offers area and speed advantages over other similar designs based on WBS and hybrid-redundant representations.

Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value

“…We have previously studied weighted-bit-set (WBS) encodings for digit sets and extended them to include the use of other two-valued digits [11]. Graphically, we use an extended dot notation: .…”

“…Logically, we use 0 for the smaller and 1 for the larger of the two twit values, a convention leading to inverted encoding of negabits (0 denotes À1 and 1 denotes 0), complementary to the common usage. Such encodings ( Table 2) have been shown to result in efficient, VLSIfriendly adder designs [11], [18].…”

“…We use a redundant representation dubbed stored-unibit-transfer, or SUT [11], where the encoding provides room in the transfer part of the leastsignificant position of the result for the three possible rounding values À1, 0, and 1. Other features of our approach include:…”

Unified Approach to the Design of Modulo-(2^n +/- 1) Adders Based on Signed-LSB Representation of Residues

“…The coexistence of posibits and negabits in the same weighted position (or "column"), in general, calls for specialized adder cells, of the types used in the wellknown Pezaris array multiplier [10]. However, if we use an inverted encoding for negabits, that is, let logical 0 (1) stand for the arithmetic value -1 (0), standard fulladder cells can handle any mix of equally weighted bits of either polarity exactly as if we had nothing but posibits [3]. The arithmetic value of a negabit X with inverted encoding equals X -1.…”

Efficient Hamming Weight Comparators for Binary Vectors Based on Accumulative and Up/Down Parallel Counters

“…We use here a simple variation of the (ν, π) encoding, which we call (ν , π) encoding, where the ν bit is inverted. This rather trivial change has been shown to produce significant savings [24] in cost and delay (and to a lesser extent, power consumption) of circuits that process binary signed digits (BSDs) in {−1, 0, 1}. These savings result from the avoidance of multiple inversions in the course of computation.…”