Wetting behavior of polymer liquid in insulation process for through silicon via

Zhao, Songfang; Zhang, Guoping; Sun, Rong; Lee, S. W. Ricky

doi:10.1109/icept.2013.6756489

Cited by 2 publications

(2 citation statements)

References 8 publications

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“…For the spin coating process, polymer liquid first wets the top surface of wafer and then flows into the vias as shown in Figure 1. From Figure 2b, it can be found that the novolac resin based glue has lower contact angle (about 25.9 o ), indicating that it has better wetting performance and is suitable for spin coating on the bare silicon substrate [7]. Compared to SiO 2 insulation layer, the polymer insulation layer has the properties of more thick at scale of 3~5 um and faster fabrication in 5~10 min.…”

Section: Resultsmentioning

confidence: 95%

Fabricating polymer insulation layer by spin-coating for through silicon vias

Zhang

Jiang

Liu

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

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This paper reports a fabrication process for the deposition of a polymer insulation layer on the sidewall of through silicon vias in wafer level packaging. The novolac resin based glue was used as precursor to prepare the insulation layer. The glue is a Newtonian fluid and has low viscosity (24 mPa*s @ 100 l/s) as well as low contact angle (25.9 o ) to silicon. The resultant polymer insulation layer has a shearing strength as high as 25.8 Kg/mm 2 . Furthermore, the polymer insulation layer exhibits good uniformity in thickness and roughness over the whole 8'' wafer. On the conformal coating of the polymer insulation layer, the Ti/Cu seed layer and Cu conductive layer were fabricated by PVD and electroplating. Therefore, all the results show that the polymer materials could be a reliable and economical solution for the TSV insulator in the view of wafer level packaging. IntroductionThree dimensional (3D) integration circuit technology affords significant promise to release the power, improve the performance and computational tradeoffs inherent in conventional planar circuit topologies, and makes through silicon via (TSV) appear to be one of the greatest technology challenges, inspiringly, the TSV technology has been successfully applied in CMOS image sensors (CIS) widely [1,2]. However, the aspect ratio of TSV for CIS is much smaller than that for interposer. Therefore, there are several options for fabricating conformal insulation layer on wafer level packaging.

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Section: Resultsmentioning

confidence: 95%

Fabricating polymer insulation layer by spin-coating for through silicon vias

Zhang

Jiang

Liu

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

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“…Therefore, the degree of adhesion between polymer liquid and sidewall should be tempered moderately. [5] Obviously, the power and time of O 2 plasma were investigated to monitor the hydrophilcity.…”

Section: Introductionmentioning

confidence: 99%

O<inf>2</inf> plasma treatment in polymer insulation process for through silicon vias

Zhuang

Jiang

Zhang

et al. 2014

2014 15th International Conference on Electronic Packaging Technology

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Through silicon via (TSV) technology has been widely applied in CMOS image sensors (CIS). This paper reports the wetting behavior of polymer liquid in the TSV insulation process by spin coating. The O 2 plasma treatment was used to increase the hydrophilicity of the substrate surface in order to reduce the adhesion between the polymer liquid and the via sidewall. This surface treatment was to ensure that the polymer liquid can enter the vias smoothly. Besides, the O 2 plasma treatment to the wafer could also improve the wetting rate and decrease the balanced contact angle. During the course of the present study, different parameters of power and time of O 2 plasma treatment were used to modify the wafer surface and the sidewall of vias. The optimal O 2 plasma treatment condition was determined with the power of 160 W and the processing time of 25 s. It was confirmed that the method of O 2 plasma treatment is beneficial to the wetting in the deposition process of the polymer insulation layer for TSVs. Keywords-through silicon via; O 2 plasma treatment; polymer liquid; insulation; adhesion 2014 15th International Conference on Electronic Packaging Technology 978-1-4799-4707-2/14/$31.00 ©2014 IEEE

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Wetting behavior of polymer liquid in insulation process for through silicon via

Cited by 2 publications

References 8 publications

Fabricating polymer insulation layer by spin-coating for through silicon vias

Fabricating polymer insulation layer by spin-coating for through silicon vias

O<inf>2</inf> plasma treatment in polymer insulation process for through silicon vias

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