What designers of wafer scale systems should know about local sparing

Abstract

Local sparing is a simple way to organize the redundancy of a fault tolerant system. A n y system can be locally spared. Furthermore, local sparing preserves both regularity and planarity. In spite of this, the potential usefulness of local sparing appears to have been overlooked. Suppose that the designer wishes to assure, with high probability, a fault-free copy of the n-element system desired. If local sparing is used then, as we prove, i) the resulting area is e( log n ) times the area of the system desired; ii) the wirelength is O( +) times the maximum wirelength in the desired system; iii) an optimal diagnosis algorithm identifies the faulty elements in @ ( n log' n ) time; iv) in optimal time @(n log n + number or wires in the desired system) , a simple configuration algorithm achieves a fault-free copy of the desired system if and only if a fault-free copy exists. We illustrate these results for arrays, binary trees, and hypercubes. In addition, v) if Y denotes the probability of achieving a fault-free copy of the system desired then, usin6 h-fold redundancy, the maximum rate at which elements can fail is ( Local sparing is simple, widely-applicable, and low-cost. A disadvantage is that, depending on the system desired, the cost may not be optimal. However, there is strong reason to prefer local sparing over global sparing, and in some cases local sparing is better than more popular approaches to configuration.

Utilizing spares in multichip modules for the dual function of fault coverage and fault diagnosis

“…These links are already in place for coverage purposes. In [7], the relationship between the amount of coverage and potential self-diagnosis in localized spares is shown to be related. We see the relationship in this example, where coverage of one node by another provides a potential test link between the 2 nodes.…”

“…A combination test vector/comparison approach has been examined in [lo] for production-level self diagnosis of wafers to avoid timely sequential wafer probing. In the theoretical work by LaForge [7], the communication links between nodes in local spares systems are examined for diagnosis capability.…”

Test vehicle for a wafer-scale field programmable gate array

“…There are also some applications where the physical placement of the cell is critical, like large sensor or transducer arrays. The kind of redundancy used then is called local sparing [16], where the spares are physically close to the original cell. For FPGAs, the physical placement of the cells is not critical because all cells are identical.…”

Spaceflight Multi-Processors with Fault Tolerance and Connectivity Tuned from Sparse to Dense

“…The test MUTEX mentioned above implies that any such schedule is at least as long as the degree δ of any vertex of D. Therefore, schedule length is at least ⎡ δ avg ⎤, with the total number of tests ½⋅n⋅δ avg (n) scaling as described in the preceding paragraph. Fortunately, we can one-factorize D into the minimum number ⎡ δ avg ⎤ of matchings, for at least two parameterizable classes of test digraphs: i) D is a directed Harary-Hayes graph G H-H (n, f ); ii) D comprises a directed Hamiltonian cycle on the blocks of locally-spared topologies G H-L (n , p, h), with f +1 vertices in each block (original analysis, for VLSI arrays, in [37] and [38]; details in Sub-appendix A.4; Figure 8 of [44] illustrates for n = 4, h = 2). The fewest timeslots to compute a syndrome is a) Θ(1), for a constant number of faults, and in the worst case; b) Θ(n), when the worst-case fault count scales as a constant fraction of n; c) Θ(log n), to almost surely diagnose or tolerate a constant fraction of IID faults, and d) Θ(1), for almost sure diagnosis or tolerance, and where we are allowed to misdiagnose as faulty an arbitrarily small fraction of healthy nodes.…”

“…This severely hampers our ability to tap the full range of tunable topologies, whose degrees can (and should, recalling discussions on pages 5 and 9) be capable of scaling with the number n of nodes. For example, the best layout we know for an n-node binary hypercube costs O(n 2 ) area, O(n) wirelength [37]. With VCSELs, we estimate that we will be able to reduce the area of binary hypercubes to between Ω(n) and O(n log n), with wirelength Θ(1).…”