What makes a design difficult to route

Alpert, Charles J.; Li, Zhuo; Moffitt, Michael D.; Nam, Gi-Joon; Roy, Jarrod A.; Téllez, Gustavo

doi:10.1145/1735023.1735028

Cited by 60 publications

(32 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A placement which is routable in the global routing stage may actually be not routable in the detailed routing stage. Works [37], [56], [57] have shown that the predictions by global router on the actual violations encountered in the final detailed routing phase are usually not accurate enough. That means a placement optimized perfectly towards global routing congestion may still be unroutable in detailed routing.…”

Section: Detailed Routability-driven Placementmentioning

confidence: 99%

Placement: From Wirelength to Detailed Routability

Chow

Young

2016

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

show abstract

Section: Detailed Routability-driven Placementmentioning

confidence: 99%

Placement: From Wirelength to Detailed Routability

Chow

Young

2016

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

show abstract

“…Given a circuit, to compute a directive assignment solution to maximize the timing improvement and to minimize the total cost. Depending on the purpose, 2 Our enhanced implementation also considers the effects of vias on the wire delay.…”

Section: Overview Of Catalystmentioning

confidence: 99%

“…Wire resistance per unit length increases quadratically with technology scaling and results in significant increases in wire delay. However, recent work [1], [2] shows that the availability of thicker wires in higher metal layers could potentially relieve this problem. At 65 nm technology, there are four 1× layers, three 2× layers and two 4× layers (Fig.…”

Section: Introductionmentioning

confidence: 99%

“…First, it is not aware of the routing congestion. The approach attempts to control the number of nets promoted to thick layers, but its guess and trial approach could still easily cause over-promotion (assigning too many nets to thick layers) in the design, which causes the design to be unroutable [2]. Second, it does not explicitly minimize the buffer usage: it may underuse the thicker layers if the timing can be closed by buffer insertion on thinner layers, with excessive buffers inserted.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

CATALYST: Planning Layer Directives for Effective Design Closure

Wei

Sze

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

Self Cite

View full text Add to dashboard Cite

Abstract-For the last several technology generations, VLSI designs in new technology nodes have had to confront the challenges associated with reduced scaling in wire delays. The solution from industrial back-end-of-line process has been to add more and more thick metal layers to the wiring stacks. However, existing physical synthesis tools are usually not effective in handling these new thick layers for design closure. To fully leverage these degrees of freedom, it is essential for the design flow to provide better communication among the timer, the router, and different optimization engines. This work proposes a new algorithm, CATALYST, to perform congestion-and timing-aware layer directive assignment. Our flow balances routing resources among metal stacks so that designs benefit from the availability of thick metal layers by achieving improved timing and buffer usage reduction while maintaining routability. Experiments demonstrate the effectiveness of the proposed algorithm. I. INTRODUCTIONPhysical synthesis is a critical component of modern design methodologies, enabling timing closure at the physical design stage. Technology scaling brings new challenges and opportunities to physical synthesis. Wire resistance per unit length increases quadratically with technology scaling and results in significant increases in wire delay. However, recent work [1], [2] shows that the availability of thicker wires in higher metal layers could potentially relieve this problem. At 65 nm technology, there are four 1× layers, three 2× layers and two 4× layers (Fig. 3). On a 2× layer, the single-width wires are 2× thicker and 2× wider than those on 1× layer, and therefore the per-unit wire resistance is reduced by roughly 4× (the per-unit capacitance is roughly similar across all layers, which is ensured by design rules including wire spacing and process specifications such as inter-layer dielectric thickness), greatly compensating for technology scaling effects. On the 2× [4×] layer, signals can roughly go 1.7× [2.5×] faster, with 2× [4.4×] reduction in buffer resources. Therefore, the difference in wire delays in different layers provides another dimension to timing optimization, beyond gate/wire sizing and buffering. Assigning timingcritical nets to thick layers can reduce area/power and improve timing closure by reducing delays and the buffer count. As illustrated in Fig. 1, the slack for a two-pin net A on a 4× layers is improved from -10 ps to 10 ps as compared to the corresponding route on the 1× layer, and the number of buffers is reduced from 7 to 1. Moreover, by using thick layers wisely, it could be shown that a 31% reduction on buffer area averaged over several industrial circuits can be achieved (Sec. VI-B). On the other hand, there are limited resources on thicker layers, and if too many nets are assigned to thicker layers, the design may not be routable or have large post-routing timing degradation.

show abstract

“…Placement, which plays a fundamental and important role in physical design, can greatly affect the quality of the routing solution and is perhaps the most powerful tool in the congestion alleviation [1].…”

Section: Introductionmentioning

confidence: 99%

Ripple: An effective routability-driven placer by iterative cell movement

He¹,

Huang²,

Xiao³

et al. 2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

In this paper, we describe a routability-driven placer called Ripple. Two major techniques called cell inflation and net-based movement are used in global placement followed by a rough legalization step to reduce congestion. Cell inflation is performed in the horizontal and the vertical directions alternatively. We propose a new method called net-based movement, in which a target position is calculated for each cell by considering the movement of a net as a whole instead of working on each cell individually. In detailed placement, we use a combination of two kinds of strategy: the traditional HPWL-driven approach and our new congestiondriven approach. Experimental results show that Ripple is very effective in improving routability. Comparing with our pervious placer, which is the winner in the ISPD 2011 Contest, Ripple can further improve the overflow by 38% while reduce the runtime is reduced by 54%.

show abstract

What makes a design difficult to route

Cited by 60 publications

References 17 publications

Placement: From Wirelength to Detailed Routability

Placement: From Wirelength to Detailed Routability

CATALYST: Planning Layer Directives for Effective Design Closure

Ripple: An effective routability-driven placer by iterative cell movement

Contact Info

Product

Resources

About