Why the long-term charge offset drift in Si single-electron tunneling transistors is much smaller (better) than in metal-based ones: Two-level fluctuator stability

Abstract

A common observation in metal-based ͑specifically, those with AlO x tunnel junctions͒ single-electron tunneling ͑SET͒ devices is a time-dependent instability known as the long-term charge offset drift. This drift is not seen in Si-based devices. Our aim is to understand the difference between these, and ultimately to overcome the drift in the metal-based devices. A comprehensive set of measurements shows that ͑1͒ brief measurements over short periods of time can mask the underlying drift, ͑2͒ we have not found any reproducible technique to eliminate the drift, and ͑3͒ two-level fluctuators ͑TLFs͒ in the metal-based devices are not stable. In contrast, in the Si-based devices the charge offset drifts by less than 0.01e over many days, and the TLFs are stable. We also show charge noise measurements in a SET device over four decades of temperature. We present a model for the charge offset drift based on the observation of nonequilibrium heat evolution in glassy materials, and obtain a numerical estimate in good agreement with our charge offset drift observations. We conclude that, while the Si devices are not perfect and defect-free, the defects are stable and noninteracting; in contrast, the interacting, unstable glasslike defects in the metal-based devices are what lead to the charge offset drift. We end by suggesting some particular directions for the improvement in fabrication, and in particular, fabrication with crystalline metal-oxide barriers, that may lead to charge offset drift-free behavior.

Stability of Single Electron Devices: Charge Offset Drift

“…A typical measurement of the charge offset drift for a metallic device is shown in Figure 3a [30]. As is plainly apparent from the data, the charge offset value wanders between 0 and 1e over the course of the measurement (and, in fact, probably wanders through several e).…”

“…This is probably a result of the increased number of gate voltages which are required to remain stable through mechanical or electrical disturbances in the tunable devices. However, this may depend on the details of fabrication since remarkable reproducibility has also been observed even after thermal cycling to room temperature [46] (see Figure 8 inset) or with months between measurements [30]. Thus, measurements of charge offset drift in the time domain reveal all-silicon devices (PADOX or electrostatic barrier devices) to be much more stable than metal devices.…”

“…Measurements of charge offset drift are not difficult to make, though care must be taken to make sure that the measurement circuit and wiring are such that they do not artificially inflate the level of charge offset drift recorded. There are two typical measurement setups for quantifying the level of charge offset drift in a particular device [30]. In the first method, a set of Coulomb blockade oscillations are repeatedly measured with a time delay between each measurement.…”

Coherent electrical rotations of valley states in Si quantum dots using the phase of the valley-orbit coupling

“…Therefore, unless this noise can be filtered out the coherence time T * 2 may be too short for quantum computation. Reliable numbers for 1/f noise in single and double Si QDs are scarce, though 1/f noise and the charge offset drift has been measured in SETs 96 and are indicative of the results to be expected in QDs. At the same time, there has been progress of late in combating the effect of noise in QD spin qubits, such as a singlet-triplet qubit via dynamical decoupling, 97 composite pulses, 98 and by growing a buried quantum dot 99 further from the interface.…”

Formation of strain-induced quantum dots in gated semiconductor nanostructures

“…3,4 Silicon QDs are also being pursued for electrical standards because charge pumps built from silicon QDs are more stable as a function of time than metallic charge pumps. 5,6 To pursue these applications, many different methods are used to create silicon QDs. 2 In this letter we will focus on one common method of creating silicon QDs: metallic gates on bulk silicon.…”