2018
DOI: 10.1177/0037549718785442
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Why we should use Min Max DEVS for modeling and simulation of digital circuits

Abstract: The delay is a very important element in modeling hardware behavior, and is realized in many hardware description languages such as ADLIB-SABLE, Verilog, and VHDL. The state of the art on hardware delay identifies four classes. In the first class, mean values are used as a precise delay element in the simulation; we found it in VHDL (VHSIC (very high speed integrated circuit) Hardware Description Language), where a single value is utilized to characterize the transport delay. In the second class, the delay is … Show more

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