Wide bus chip-to-chip interconnection technology using fine pitch bump joint array for 3D LSI chip stacking

Aoyagi, Masahiro; Imura, Fumito; Nemoto, Shunsuke; Watanabe, Naoya; Kato, Fumiki; Kikuchi, Katsuya; Nakagawa, Hiroshi; Hagimoto, Michiya; Uchida, Hirohisa; Matsumoto, Yukoh

doi:10.1109/icsj.2012.6523418

Cited by 7 publications

(3 citation statements)

References 2 publications

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“…Large signal transmission performance of 51.2 Gbps (1024 bit • 50 MHz) was demonstrated under a low power consumption condition of 87 mW. [36] [37] For the interface circuit composed of a 0.25 μm node CMOS device that operates at power voltage of 2.5 V, large capacity transmission was achieved at sufficiently low power consumption. Further power saving can be expected by using a finer node CMOS device.…”

Section: Verification Randd By Design Prototyping and Evaluation Usinmentioning

confidence: 99%

Developing a leading practical application for 3D IC chip stacking technology

Aoyagi

Imura

Kato

et al. 2016

Synthesiology English edition

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IC technologies, and the attempt to increase the integration density seemed to face the limit. The three-dimensional IC chip stacking technology whereby the IC devices are stacked vertically and packaged is one of the solutions, and expectation for it is rising recently as a technology for semiconductor device stacking that enables the increase of integration density for semiconductor ICs. Therefore, we established the fundamental technology for high-density high-integration electronic hardware construction required for 3D IC chip stacking, and we are working on the R&D of the application phase to create the flow of application system development, while engaging in technical support of massproduction technology that, in practice, should be undertaken by leading companies. Advancement of electronic hardware system integration technology by 3D IC chip stacking and the goal of this researchFirst, we shall review the recent development trends of the electronic hardware system integration technology that advanced the manufacturing technology in response to the demand for high density and high integration to enhance the system performance. The system integration method called the system in package (SIP) Term 1 is gaining attention, where several IC chips are stacked in a semiconductor IC package to integrate them into a certain size electronic system. This method enables stacking in the vertical direction that is different from the planar integration technology of -How to progress from fundamental technology to application technology-3D IC chip stacking technology, which is a technology to vertically stack multiple IC chips such as CMOS, MEMS and power IC chips, is expected to be one of future electronic device integration technologies, because integration along the additional vertical dimension affords efficient use of space and innovation of system architecture. We developed fundamental technology of high density integration for 3D IC chip stacking. To accelerate industrial applications of this technology, a mass-production process was developed in collaboration with a manufacturing equipment company.Research paper : Developing a leading practical application for 3D IC chip stacking technology (M.AOYAGI et al.) − 2 − Authors Masahiro AOYAGI G r a d u a t e d f r o m t h e D e p a r t m e n t of Elect ronic Engineer ing, Facult y of E ng i n e e r i ng , Na goy a I n s t it u t e of Tech nolog y i n 1982. Joi ned t he Electrotechnical Laboratory, Agency of Industrial Science and Technology, Ministr y of Inter national Trade and Industry in 1982. Engaged in the R&D of integrated circuit and system for superconductor device, high-speed high-density packaging system tech nolog y, and others. Obt ained doctorate (Engineering) from the Nagoya

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Section: Verification Randd By Design Prototyping and Evaluation Usinmentioning

confidence: 99%

Developing a leading practical application for 3D IC chip stacking technology

Aoyagi

Imura

Kato

et al. 2016

Synthesiology English edition

Self Cite

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Section: Introductionmentioning

confidence: 99%

“…The cone shape bumps are suitable for a thermocompression bump joint process with low temperature and low load force, where the bumps are easy to collapse with loading due to the pointed structure. High yield micro bump joints can be obtained [3][4].The cone shape bumps can be fabricated by lift-off process using thick photo resist with 10 m diameter bump pattern. The cross section of the bump pattern must have vertical straight side wall.…”

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confidence: 99%

Development of micro bump joints fabrication process using cone shape Au bumps for 3D LSI chip stacking

Imura

Watanabe

Nemoto

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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3D LSI chip stacking technology have been developed using cone shape Au micro bumps fabricated by nanoparticle deposition method. The cone shape bumps with less than 10 m diameter are suitable for a thermocompression bump joint process with low temperature and low load force. High yield micro bump joints can be obtained. In this study, the property evaluation of the cone shape bumps, and the cone shape bump joints were investigated in details. The collapsed bump height and the electrical resistance can be controlled by compression force. The low resistance (average 8.6 m bump joint with a 10 m diameter cone shape Au bump was successfully achieved. Introduction3D system integration technologies are playing an important role in system miniaturization and performance improvement of future LSI system technology. 3D LSI chip stacking technology have been developed in AIST using cone shape Au micro bumps fabricated by nanoparticle deposition method [1-2]. The cone shape bumps are suitable for a thermocompression bump joint process with low temperature and low load force, where the bumps are easy to collapse with loading due to the pointed structure. High yield micro bump joints can be obtained [3][4].The cone shape bumps can be fabricated by lift-off process using thick photo resist with 10 m diameter bump pattern. The cross section of the bump pattern must have vertical straight side wall.During the nanoparticle deposition, sample cooling is very important to assure the lift-off process. The target sample should moves continuously during the deposition in order to avoid the heat concentration.A set of a plane pad and a cone shape bump is used for the micro bump joint formation. The cone shape bump can smoothly collapse by thermocompression method without buckling. The collapsed bump height and the electrical resistance can be controlled by compression force. The temperature range of the bonding process is from RT to 200 ºC. The bump hardness decreases with increasing the process temperature.In this paper, we report about the nanoparticle deposition system, the cone shape bump formation process, the property evaluation of the cone shape bumps, the bump joint formation process, and the property evaluation of the cone shape bump joints in details.

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