A 3D thermal model based on finite elements has been developed for the analysis of the thermal resistance of I d ' heterojunction bipolar transistors. The model was verified by comparing simulated and experimental results. The simulations also show that the maximum temperature in the device can be significantly higher than the experimentally determined base-emitter junction temperature. By applying scaling laws, a road map for 80Gbit/s and 160Gbit/s devices is presented. Simulations show that devices suitable for I6OGbit/s circuits will be thermally possible if the InGaAs etch stop or contacting layer is removed from the sub collector.I Introduction 40Ghitk integrated circuits (ICs) are becoming commercially available. Two major competing technologies are SiGe heterojunction bipolar transistors (HBTs) and InP HBTs. While very high mm wave power gains have been obtained with single heterojunction devices (SHBT), they suffer from low breakdown voltages and high thermal resistance because of the narrow hand gap InGaAs collector. To overcome these inherent problems, a double heterosmcture bipolar transistor (DHBTs), which has an InP collector, can be used. Devices of this kind have been reported with a fm in excess of 4SOGHz [2,3]. These results indicate that DHBTs have potential applications in 80Gbitk and 16OGhitk ICs. This is reinforced by recent observations of frequency dividers operating above 80GHz [4,5]. As device design is modified for 80-160Gbitsis applications, the current density within the device will greatly increase resulting in higher device temperatures and so accurate thermal design is critical for accurate circuit simulation and reliability studies.Thermal modeling of HBTs has, to date, centered on power amplifiers [6]. These studies have concentrated on modeling the beat flow in the substrate using a semi-analytical approach developed for Si BJT's [7]. The method does not account for (1) the temperature gradients within tbe device wbicb are significant in sub-micron HBT's or (2) heat flow through the emitter metalisation which can be high as 20% of the total heat dissipated.Before circuits can he marketed, the device reliability must be assessed and this has driven an interest in the thermal resistance of InP HBTs. [9,10] For 80 and 160 and probably 4OGbit/s applications, DHBTs will be used because of their lower thermal resistance. This paper examines the thermal performance of devices for the 80 and 160 GbiUs applications by modeling the heat flow in 3D.
Device ScalingTo achieve high-speed performance, an increase in the current density (J) will allow a device with a smaller collectorbase junction area to be used in the circuit, so reducing Cbc. However, J cannot he increased indefinitely because of the Kirk Effect.If the collector doping No is chosen so that the collector is fully depleted at zero bias current and the applied V,, the maximum current density through the emitter junction is approximately given by
0-7803-7704-4/03/$17.0oo2o03 IEEEwhere E is the dielectric constant of the collector...