Winograd-Based Real-Time Super-Resolution System on FPGA

Shi, Bizhao; Tang, Zhucheng; Luo, Guojie; Jiang, Ming

doi:10.1109/icfpt47387.2019.00083

Cited by 15 publications

(20 citation statements)

References 11 publications

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“…The experiments, performed on the Xilinx XC7K410T field programmable gate array (FPGA) chip, demonstrated the benefits of the proposed approach in terms of area occupancy and energy saving over several state-of-the-art counterparts. In fact, the new accelerator exhibited a logic resource requirement and a power consumption up to ~63% and ~48% lower, respectively, than previous designs [ 11 , 13 , 14 , 15 , 16 , 17 ]. The adopted parallelism and the achieved 227 MHz running frequency allow the above advantages to be obtained without compromising the competitiveness of the proposed design in terms of speed performance.…”

Section: Introductionmentioning

confidence: 92%

“…Unfortunately, these characteristics may represent a bottleneck for those application scenarios in which real time and low power are mandatory. For this reason, designing ad-hoc hardware accelerators suitable for exploitation also within time- and power-constrained operating environments has recently received a great deal of attention [ 11 , 12 , 13 , 14 , 15 , 16 , 17 , 19 , 20 , 21 , 22 , 23 ]. Among the possible hardware realization platforms, FPGAs are widely recognized as powerful solutions [ 11 , 13 , 15 , 17 , 20 ] for merging the benefits from custom hardware designs, such as computational parallelism and limited energy consumption, with the strengths of software designs, including reconfigurability and short time to market.…”

Section: Background and Related Workmentioning

confidence: 99%

“…While several of the existing hardware designs support both CONVs and TCONVs [ 11 , 13 , 14 , 15 , 16 , 17 , 19 , 21 ], some of them are tailored to accomplish only TCONVs [ 12 , 22 , 23 ]. As an example, the FPGA accelerator proposed in our previous work [ 12 ] deals with the input-oriented method (IOM) to reduce, or completely avoid, useless operations, corresponding to multiplications by zero, introduced by the conventional zero-TCONVs’ up-sampling approach.…”

Section: Background and Related Workmentioning

confidence: 99%

“…The designs recently presented in [ 11 , 13 , 14 , 15 ] overcome the aforementioned issues by exploiting uniform accelerators for both CONVs and TCONVs. Starting from an analysis of the input-oriented method (IOM), and with the objective of avoiding overlapping on input activations, the computational scheme proposed in [ 11 ] performs an inverse mapping on the filter coefficients.…”

Section: Background and Related Workmentioning

confidence: 99%

“…Moreover, in comparison to CONVs, TCONV layers require more complex strategies to access data memory, and make skipping operations necessary to manage the incoming pixels properly [ 12 ]. In order to overcome the aforementioned issues, several algorithms have been proposed [ 11 , 13 , 14 , 15 ] to transform TCONV into CONV layers by pre-processing either the input data or the filter coefficients. However, when implemented in hardware, these methods can show several drawbacks.…”

Section: Introductionmentioning

confidence: 99%

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Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions

2021

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Nowadays, computer vision relies heavily on convolutional neural networks (CNNs) to perform complex and accurate tasks. Among them, super-resolution CNNs represent a meaningful example, due to the presence of both convolutional (CONV) and transposed convolutional (TCONV) layers. While the former exploit multiply-and-accumulate (MAC) operations to extract features of interest from incoming feature maps (fmaps), the latter perform MACs to tune the spatial resolution of the received fmaps properly. The ever-growing real-time and low-power requirements of modern computer vision applications represent a stimulus for the research community to investigate the deployment of CNNs on well-suited hardware platforms, such as field programmable gate arrays (FPGAs). FPGAs are widely recognized as valid candidates for trading off computational speed and power consumption, thanks to their flexibility and their capability to also deal with computationally intensive models. In order to reduce the number of operations to be performed, this paper presents a novel hardware-oriented algorithm able to efficiently accelerate both CONVs and TCONVs. The proposed strategy was validated by employing it within a reconfigurable hardware accelerator purposely designed to adapt itself to different operating modes set at run-time. When characterized using the Xilinx XC7K410T FPGA device, the proposed accelerator achieved a throughput of up to 2022.2 GOPS and, in comparison to state-of-the-art competitors, it reached an energy efficiency up to 2.3 times higher, without compromising the overall accuracy.

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