Wirelength minimization for min-cut placements via placement feedback

Abstract

Abstract-DNA probe arrays, or DNA chips, have emerged as a core genomic technology that enables cost-effective gene expression monitoring, mutation detection, single nucleotide polymorphism analysis, and other genomic analyses. DNA chips are manufactured through a highly scalable process called very largescale immobilized polymer synthesis (VLSIPS) that combines photolithographic technologies adapted from the semiconductor industry with combinatorial chemistry. Commercially available DNA chips contain more than half a million probes and are expected to exceed 100 million probes in the next generation. This paper is one of the first attempts to apply very large scale integration (VLSI) computer-aided design methods to the physical design of DNA chips, where the main objective is to minimize total border cost (i.e., the number of nucleotide mismatches between adjacent sites).By exploiting analogies between manufacturing processes for DNA arrays and for VLSI chips, the authors demonstrate the potential for transfer of methodologies from the 40-year-old field of electronic design automation to the newer DNA array design field. The main contributions of this paper are the following. First, it proposes several partitioning-based algorithms for DNA probe placement that improve solution quality by over 4% compared to best previously known methods. Second, it gives a new design flow for DNA arrays, which enhances current methodologies by adding flow awareness to each optimization step and introducing feedback loops. Third, it proposes solution methods for new formulations integrating multiple design steps, including probe selection, placement, and embedding. Finally, it introduces new techniques to experimentally evaluate the scalability and suboptimality of existing and newly proposed probe placement algorithms. Interestingly, the authors find that DNA placement algorithms appear to have better suboptimality properties than those recently reported for VLSI placement algorithms (

Full Custom Layout Optimization Using Minimum distance rule, Jogs and Depletion sharing

“…Even though the techniques such as recursive top down partitioning, iterative refinement, embedded multilevel optimizations, path-based algorithms and routability optimization are leading to better placement [5], those existing placement solutions are far from optimal. Repartitioning [6] methods proposed by introducing placement feedback controllers improve partitioning result. Improved mincut bisection leads to better placement and less congestion which enhances the quality of the layout in post layout stage.…”

Practical Problems in VLSI Physical Design Automation

“…The authors of [Kahng and Reda, 2006] improved the accuracy of terminal propagation by a "placement feedback" mechanism. At each level of mincut placement, all blocks are partitioned first.…”