WITHDRAWN: Comparative analysis on low power SRAMs

Leela, Moru; Rooban, S.; Joshitha, C.

doi:10.1016/j.matpr.2020.11.140

Cited by 1 publication

(1 citation statement)

References 14 publications

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“…Triple threshold voltage CMOS technology design is carried on 6T, 7T & 8T based cells in (4) .7T based SRAM cell designing based on SVL and I-SVL is done in (5) (6) . A high speed and Low leakage 6T SRAM cell is proposed by adopting MTCMOS method (7,8) .A comparative survey on SRAM has been carried using distinct Low Power techniques (9) . A New 7T based SRAM Memory cell has been proposed with improved performance during read operation (10) .…”

Section: Introductionmentioning

confidence: 99%

Analysis of 7T SRAM Cell Based on MTCMOS, SVL and I-SVL Technique

Kumar¹,

Kariyappa²

2022

IJST

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Objective: To design and propose an optimized Volatile 7T based SRAM cell in terms of leakage currents and dynamic power. Methods: The methodology involved is Multi threshold Voltage CMOS (MTCMOS), Self Controllable Voltage Level (SVL) and Improved Self Controllable Voltage Level (I-SVL). Findings: The proposed work demonstrates that 7T based SRAM cell using I-SVL method is efficient in terms of leakage currents and dynamic power. Also, Comparative Leakage current and dynamic power analyses are done between MTCMOS, SVL, and I-SVL methods The Proposed work based on I-SVL is significant than the MTCMOS and SVL Technique. All the circuits are developed using the Cadence virtuoso tool and spectre simulator is used to carry out the simulation. Novelty: The paper proposes Low power Volatile Memory cell based on 7T with improvements in leakage and dynamic power values in comparison with the earlier literatures. The proposed I-SVL based cell is 89% and 85% efficient in terms of dynamic power in comparison with the earlier references.

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