World-most energy-efficient MRAM technology for non-volatile RAM applications

Lee, T. Y.; Lee, J. M.; Kim, M. K.; Oh, Jun‐Seok; Lee, Jeong‐Whan; Jeong, Hongsil; Jang, Pilsung; Joo, Minwoo; Suh, Kyung Soo; Han, Shin-Hee; Jeong, Dong Seop; Kai, T.; Jeong, Jooyeon; Park, J.-H.; Lee, J. H.; Park, Y. H.; Chang, Eun‐Chul; Park, Y. K.; Shin, Hong-Jae; Ji, Yumi; Hwang, Seongtaek; Nam, Kwangwoo; Kwon, B. S.; Cho, M. K.; Seo, Bong-Gun; Song, Yoo Sung; Koh, G.H.; Lee, K.; Lee, J.-H.; Jeong, Goojin

doi:10.1109/iedm45625.2022.10019430

Cited by 22 publications

(4 citation statements)

References 3 publications

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“…Samsung reported STT-MRAM macros designed for energyefficient stand-alone memories 55 . Fabricated on 28 nm and 14 nm techno logy nodes, the macros demonstrated almost unlimited endurance (>10 14 cycles) with a write power of 27 mW and a read power of 14 mW.…”

Section: Stt-mram and Sot-mram Prototype Chipsmentioning

confidence: 99%

High-speed emerging memories for AI hardware accelerators

Lu,

Lee,

Kim

et al. 2024

Nat Rev Electr Eng

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Applications of artificial intelligence (AI) necessitate AI hardware accelerators able to efficiently process data-intensive and computationintensive AI workloads. AI accelerators require two types of memory: the weight memory that stores the parameters of the AI models and the buffer memory that stores the intermediate input or output data when computing a portion of the AI models. In this Review, we present the recent progress in the emerging high-speed memory for AI hardware accelerators and survey the technologies enabling the global buffer memory in digital systolic-array architectures. Beyond conventional static random-access memory (SRAM), we highlight the following device candidates: capacitorless gain cell-based embedded dynamic random-access memories (eDRAMs), ferroelectric memories, spin-transfer torque magnetic random-access memory (STT-MRAM) and spin-orbit torque magnetic random-access memory (SOT-MRAM). We then summarize the research advances in the industrial development and the technological challenges in buffer memory applications. Finally, we present a systematic benchmarking analysis on a tensor processing unit (TPU)-like AI accelerator in the edge and in the cloud and evaluate the use of these emerging memories. Sections• Leading edge node SRAM is still a competitive high-performance technology for AI hardware in the cloud, whereas emerging memories exhibit more advantages in AI hardware at the edge where minimizing the stand-by leakage power is critical.Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

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Section: Stt-mram and Sot-mram Prototype Chipsmentioning

confidence: 99%

High-speed emerging memories for AI hardware accelerators

Lu,

Lee,

Kim

et al. 2024

Nat Rev Electr Eng

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“…These torques due to a gradient of the magnetization are modeled by the ZL expression. If the spin dephasing length is taken into account in [2], the expression for the bulk torque ( 8) must be generalized. We generalize the ZL torque to include λ φ using the following expression: [4] ϵ = ( λ J / λ sf ) 2 and ϵ = ( λ J / λ φ ) 2 .…”

Section: [2a]mentioning

confidence: 99%

“…If the spin dephasing length is taken into account in [2], the expression for the bulk torque ( 8) must be generalized. We generalize the ZL torque to include λ φ using the following expression: [4] ϵ = ( λ J / λ sf ) 2 and ϵ = ( λ J / λ φ ) 2 . This expression can be derived from the spin accumulation by assuming gradS=0.…”

Section: [2a]mentioning

confidence: 99%

“…Emerging spin-transfer torque magnetoresistive random access memory (STT-MRAM) is attractive for stand-alone and embedded applications. STT-MRAM is nonvolatile, operates fast, and possesses excellent endurance (1), (2), (3). STT-MRAM is compatible with CMOS technology and can be integrated during the back-end-of-line process This makes STT-MRAM promising for automotive and IoT applications, microcontrollers, frame buffer memory, and last level cache.…”

Section: Introductionmentioning

confidence: 99%

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Accurate Torque Evaluation in Elongated Ultra-Scaled STT-MRAM Devices

Fiorentini¹,

Pruckner²,

Goes³

et al. 2023

ECS Trans.

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We compute the spin torque acting on elongated magnetic layers inrecently proposed ultra-scaled STT-MRAM devices. For thispurpose we evaluate the non-equilibrium spin accumulation bysolving the coupled spin and charge transport equations. This goesbeyond the Slonczewski torque approximation which describestorques localized at the interface of the tunnel barrier and themagnetic free layer as well as the Zhang-Li torque approximationmodeling the torque acting on a magnetic texture (a domain wall)in the layer’s bulk. We show that the torque contributions frominterface and bulk are not independent from each other and ourgeneralized approach is necessary to accurately model the torquein the presence of a magnetic domain wall inside the magnetic freelayer. We implemented a numerical solution of the spin and chargetransport equations in a finite element-based framework.

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