Worst-Case Execution Time Aware Compilation Techniques for Real-Time Systems

Lokuciejewski, Paul; Marwedel, Peter

doi:10.1007/978-90-481-9929-7

Cited by 26 publications

(12 citation statements)

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“…It enables safe WCET upper-bounds to be derived without actually running the program on the target platform while still considering the influence of the state changes in the underlying hardware [13]. State changes include, e.g.…”

Section: A Static Wcet Analysis Techniquesmentioning

confidence: 99%

Methodologies for the WCET Analysis of Parallel Applications on Many-Core Architectures

Nélis

Yomsi

Pinho

2015

2015 Euromicro Conference on Digital System Design

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There is an increasing eagerness to deploy and execute parallel applications on many-core infrastructures, preserving the time-predictability of the execution as required by real-time practices to upper-bound the response time of the embedded application. In this context, the paper discusses the application of the currently-available WCET analysis techniques and tools on such platforms and with highly parallel activities. After discussing the pros and cons of all different methodologies for WCET analysis, we introduce a new approach that is developed within the P-SOCRATES project. Abstract-There is an increasing eagerness to deploy and execute parallel applications on many-core infrastructures, preserving the time-predictability of the execution as required by real-time practices to upper-bound the response time of the embedded application. In this context, the paper discusses the application of the currently-available WCET analysis techniques and tools on such platforms and with highly parallel activities. After discussing the pros and cons of all different methodologies for WCET analysis, we introduce a new approach that is developed within the P-SOCRATES project.

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Section: A Static Wcet Analysis Techniquesmentioning

confidence: 99%

Methodologies for the WCET Analysis of Parallel Applications on Many-Core Architectures

Nélis

Yomsi

Pinho

2015

2015 Euromicro Conference on Digital System Design

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“…Statements: for back-annotation [26], the execution time of statement will be assigned as the statement attribute.…”

Section: Defining the Components Of Purposed Representationmentioning

confidence: 99%

A Xml-based Representation Of Timing Information For Wcet Analysis

Parsa

Sakhaei-nia

2014

J. Math. Computer Sci.

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The Worst-Case Execution Time (WCET) analysis is an important stage in development process and verification of hard real-time systems. In this article the use of XML as a standard for exchanging timing information amongst timing analysis tools is proposed. Timing information resulted from automatic analysis of programs can be represented in XML format. Considering the type of information required for estimating the worst case execution time of programs, a set of XML tags is offered in this paper. Timing information resulted from analyzing a program by a timing analysis tool could be annotated within the program. The annotated code could be simply applied by other tools for relatively more accurate estimation of the worst case execution times. The paper also clears the way for future studies on using XML-based representation for extraction of information.

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“…In this context, the work of Knijnenburg should be mentioned, too. Taking worst‐case execution time into account, Lokuciejewski and Marwedel have explored compiler optimizations for real‐time systems.…”

Section: Related Workmentioning

confidence: 99%

Finding near‐perfect parameters for hardware and code optimizations with automatic multi‐objective design space explorations

Jahr

Calborean

Vintan

et al. 2012

Concurrency and Computation

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SummaryIn the design process of computer systems or processor architectures, typically many different parameters are exposed to configure, tune, and optimize every component of a system. For evaluations and before production, it is desirable to know the best setting for all parameters. Processing speed is no longer the only objective that needs to be optimized; power consumption, area, and so on have become very important. Thus, the best configurations have to be found in respect to multiple objectives. In this article, we use a multi‐objective design space exploration tool called Framework for Automatic Design Space Exploration (FADSE) to automatically find near‐optimal configurations in the vast design space of a processor architecture together with a tool for code optimizations and hence evaluate both automatically. As example, we use the Grid ALU Processor (GAP) and its postlink optimizer called GAPtimize, which can apply feedback‐directed and platform‐specific code optimizations. Our results show that FADSE is able to cope with both design spaces. Less than 25% of the maximal reasonable hardware effort for the scalable elements of the GAP is enough to achieve the processor's performance maximum. With a performance reduction tolerance of 10%, the necessary hardware complexity can be further reduced by about two‐thirds. The found high‐quality configurations are analyzed, exhibiting strong relationships between the parameters of the GAP, the distribution of complexity, and the total performance. These performance numbers can be improved by applying code optimizations concurrently to optimizing the hardware parameters. FADSE can find near‐optimal configurations by effectively combining and selecting parameters for hardware and code optimizations in a short time. The maximum observed speedup is 15%. With the use of code optimizations, the maximum possible reduction of the hardware resources, while sustaining the same performance level, is 50%.Copyright © 2012 John Wiley & Sons, Ltd.

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Worst-Case Execution Time Aware Compilation Techniques for Real-Time Systems

Cited by 26 publications

References 0 publications

Methodologies for the WCET Analysis of Parallel Applications on Many-Core Architectures

Methodologies for the WCET Analysis of Parallel Applications on Many-Core Architectures

A Xml-based Representation Of Timing Information For Wcet Analysis

Finding near‐perfect parameters for hardware and code optimizations with automatic multi‐objective design space explorations

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