Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory

Abstract

We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4bits/cell and a 32kb memory page at 2bits/cell are experimentally demonstrated. Introduction Phase change memory (PCM) is widely considered to be a potential next-generation non-volatile solid-state memory [1-3]. In addition to its superior write speed compared to 0.2pm -flash, PCM offers a large signal margin between its -crystalline and amorphous states. This wide dynamic range Fig. 2: TEM image of phase-change element (PCE), with underlying also opens the door for multi-level cells (MLC). In this paper, TiN heater on top of W contact. The phase-change material and the we explore MLC write algorithms for up to 16 levels in small o T test arrays, and then demonstrate a 4-level, 32kbit page being overln Tiner are coNnected ubinEs thr a via.part of an experimental memory chip. transferred into the TiN layer using RIB. After strip, oxide isolation is deposited and planarized, exposing the top of the Integration Scheme pillar electrode. The Ge2Sb2Te5 and TiN top electrode layers The memory cell consists of a pillar-heater phase change are then deposited, patterned into islands and encapsulated element (PCE) in series with an access nMOSFET (180nm with dielectric. Top contacts and metallization lines are CMOS technology). As shown in Fig. 1, the 50nm bottom formed using a standard Cu damascene process. Fig. 2 shows electrode heater is fabricated in a subtractive process from a a TEM cross-section of the finished pillar-heater PCE. 75nm thick TiN layer directly deposited over the W contacts.

Approximate storage in solid-state memories

“…While some MLC write techniques use different durations for differently sized pulses [3,27,28], we expect the pulses to have approximately the same average time in aggregate. Previous work, for example, has assumed that each step takes 250 nanoseconds [19,33].…”

W-2W Current Steering DAC for Programming Phase Change Memory

“…It exhibits superior performance when compared to Flash memory due to its scalability and fast read/write speeds [1]- [4]. PCM also provides a wide dynamic range of operation because of the potential for a large signal margin between the programmed (low resistance or SET) and erased (high resistance or RESET) states, providing the possibility of multilevel cell (MLC) operation [5]. Many approaches have been proposed to enhance the write performance and obtain a better distribution of resistance between SET and RESET states across the memory array for both single and multilevel cell operation [1]- [5].…”

“…PCM also provides a wide dynamic range of operation because of the potential for a large signal margin between the programmed (low resistance or SET) and erased (high resistance or RESET) states, providing the possibility of multilevel cell (MLC) operation [5]. Many approaches have been proposed to enhance the write performance and obtain a better distribution of resistance between SET and RESET states across the memory array for both single and multilevel cell operation [1]- [5]. This paper introduces the compact W-2W binary-weighted current steering Digital-to-Analog Converter (DAC) proposed to efficiently program the single and multilevel PCM cells.…”

Approximate Storage in Solid-State Memories

“…We model a 4-level (2-bit) PCM cell. To calibrate the write model, we start from an average write time of 3 cycles as suggested by Nirschl et al [27] and a target RBER of 10 −8 . We need values for the parameters T and P that match these characteristics.…”