Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays

Abstract

Deep neural networks are biologically-inspired class of algorithms that have recently demonstrated state-of-the-art accuracy in large scale classification and recognition tasks. Hardware acceleration of deep networks is of paramount importance to ensure their ubiquitous presence in future computing platforms. Indeed, a major landmark that enables efficient hardware accelerators for deep networks is the recent advances from the machine learning community that have demonstrated the viability of aggressively scaled deep binary networks. In this paper, we demonstrate how deep binary networks can be accelerated in modified von-Neumann machines by enabling binary convolutions within the SRAM array. In general, binary convolutions consist of bit-wise XNOR followed by a populationcount (popcount). We present two proposals − one based on charge sharing approach to perform vector XNORs and approximate popcount and another based on bit-wsie XNORs followed by a digital bit-tree adder for accurate popcount. We highlight the various trade-offs in terms of circuit complexity, speed-up and classification accuracy for both the approaches. Few key techniques presented as a part of the manuscript is use of low-precision, low overhead ADC, to achieve a fairly accurate popcount for the charge-sharing scheme and proposal for sectioning of the SRAM array by adding switches onto the read-bitlines, thereby achieving improved parallelism. Our results on a benchmark image classification dataset CIFAR-10 on a binarized neural network architecture show energy improvements of 6.1× and 2.3× for the two proposals, compared to conventional SRAM banks. In terms of latency, improvements of 15.8× and 8.1× were achieved for the two respective proposals.

HadaNets: Flexible Quantization Strategies for Neural Networks

“…A majority of current hardware implementations are variants of von-Neumann machines [1]. In such machines, the memory and computation blocks are separate.…”

10T SRAM Computing-in-Memory Macros for Binary and Multibit MAC Operation of DNN Edge Processors

“…This work performs 4096 operations per cycle and achieves a throughput of 278.2 GOPS; the 6T bit-cell is susceptible to the write disturb. This problem can be addressed by adding more transistors or capacitors into the bit-cell, such as Xcel-RAM [20], XNOR-SRAM [22], and C3SRAM [23]. The Xcel-RAM approach [20] uses 10T bit-cell and performs binary MAC operation between the weight and input that are stored in two different rows.…”

A System-Level Exploration of Binary Neural Network Accelerators with Monolithic 3D Based Compute-in-Memory SRAM

“…In addition, BNNs replace expensive MACs with bitwise XNOR followed by population count (popcount) computations; XNOR followed by popcount computation is called as XNOR-and-accumulation (XAC). Thus, BNNs are known to be suitable for resource-and energy-constrained embedded systems compared to CNNs, by reducing the computational complexity as well as the memory footprint with minimal degradation in accuracy (less than 10% [2]).…”

“…Thanks to both (1) and (2), CiM_SRAM (M3D_4L) had smaller subarrays, which eventually reduced the length of the routing wires between subarrays.…”