XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

Yin, Shihui; Jiang, Zhewei; Seo, Jae-sun; Seok, Mingoo

doi:10.1109/jssc.2019.2963616

Cited by 278 publications

(111 citation statements)

References 22 publications

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“…Jeloka et al [4] use standard push-rule 6T SRAM cells as TCAM to reduce the cell area, For IM-DP, several novel bit-cells have been proposed. XNOR-SRAM [9] employs a 12T bit-cell to compute MAC based on the resistive voltage divider formed by access transistors. Yu et al [10] use an 8T bit-cell to support current-mode accumulation.…”

Section: B Related Workmentioning

confidence: 99%

“…Besides TCAM, deep neural networks (DNNs) also cost considerable delay and power using traditional computing paradigms due to frequent memory fetch to perform the dot product (also called multiply-and-accumulate, or MAC) operation. CIM solutions for DNNs [9]- [13] can improve the throughput and energy efficiency by performing massively parallel MAC operations inside the memory array, eliminating costly data transfer.…”

Section: Introductionmentioning

confidence: 99%

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A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

Chen

Kim

et al. 2021

IEEE Open J. Circuits Syst.

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Resistive random access memory (ReRAM)-based computing in-memory (CIM) is a promising solution to overcome the von-Neumann bottleneck in conventional computing architectures. We propose a reconfigurable ReRAM architecture using a novel 4T2R bit-cell that supports non-volatile storage and two types of CIM operations: i) ternary content addressable memory (TCAM) and ii) in-memory dot product (IM-DP) for neural networks. The proposed 4T2R cell occupies a smaller area than prior SRAMbased CIM bit-cells. A 128 × 128 ReRAM macro is designed in 40nm CMOS technology. For TCAM operations, it allows a search word-length of 128 bits. For IM-DP operations, it can compute parallel dot products using binary inputs and ternary weights. The simulated search delay for TCAM operation is 0.92 ns at VDD = 0.9 V and the simulated energy efficiency for IM-DP operation is 223.6 TOPS/W at VDD = 0.7 V. Monte-Carlo simulations show a standard deviation of 4.9% in accumulate operation for IM-DP which corresponds to a classification accuracy of 95.7% on the MNIST dataset and 81.7% on the CIFAR-10 dataset. INDEX TERMS Resistive random access memory (ReRAM), ternary content addressable memory (TCAM), computing in-memory (CIM), reconfigurable architecture.

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Section: B Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

Chen

Kim

et al. 2021

IEEE Open J. Circuits Syst.

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show abstract

“…Moreover, on-chip training is also possible with SRAM based CIM architectures [19]. Most of today's SRAM CIM prototypes [20][21][22] targeted at demonstrating inference or on-chip training functionality or improving performance, while the security challenges in the SRAM-CIM designs are largely unexplored.…”

Section: Sram-based Cimmentioning

confidence: 99%

Xor-Cim

Huang

Jiang

Peng

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…In‐memory computing is another interesting topic to resolve the bottleneck of off‐chip traffic of CNN computation. There have been some published works [44, 45] that support existing neural networks with a limited set of applications. This approach uses different techniques and is in parallel to the sparse CNN accelerator research.…”

Section: Related Workmentioning

confidence: 99%

Dataflow and microarchitecture co‐optimisation for sparse CNN on distributed processing element accelerator

Pham

Lai

2020

IET Circuits, Devices & Systems

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Accelerators that utilise the sparsity of both activation data and network structure of convolutional neural networks (CNNs) have demonstrated efficient processing of CNNs with superior performance. Previous research studies have shown three critical design concerns when designing accelerators for sparse CNNs, including data reuse, parallel computing performance, and effective sparse computation. These factors were each used in the previous accelerator designs, but none of the designs have considered all the factors at the same time. This study provides analytical approaches and experimental results to reveal the insight of accelerator design for sparse CNNs. The authors have shown that the architectural aspects need to be all considered to avoid performance pitfalls, including their mutual effects. Based on the proposed analytical approach, they proposed enhancement techniques and co-designed among the factors discussed in this study. The improved architecture shows up to 1.5× data reuse and/or 1.55× performance improvement in comparison with state-of-the-art sparse CNN accelerators while still maintaining equal area and energy cost.

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XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

Cited by 278 publications

References 22 publications

A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

Xor-Cim

Dataflow and microarchitecture co‐optimisation for sparse CNN on distributed processing element accelerator

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