2017 17th International Conference on Application of Concurrency to System Design (ACSD) 2017
DOI: 10.1109/acsd.2017.22
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Xprova: Formal Verification Tool with Built-in Metastability Modeling

Abstract: This work is licensed under a Creative Commons Attribution-NonCommercial 3.0 Unported License Newcastle University ePrints-eprint.ncl.ac.uk

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“…(i) We propose a transformation to convert asynchronous circuits into synchronous models, and describe methods to encode and check correctness properties using these models with synchronous verification tools. (ii) We report the results of using this methodology with two verification tool for synchronous logic; Cadence Incisive Formal (commercial) and Xprova [5] (academic), cross-validating the results with MPSAT [6] and a custom tool (ESSET) which we developed for this purpose. (iii) We present a verification flow and use case example of mixed sync-async verification.…”
Section: B Contributionsmentioning
confidence: 99%
“…(i) We propose a transformation to convert asynchronous circuits into synchronous models, and describe methods to encode and check correctness properties using these models with synchronous verification tools. (ii) We report the results of using this methodology with two verification tool for synchronous logic; Cadence Incisive Formal (commercial) and Xprova [5] (academic), cross-validating the results with MPSAT [6] and a custom tool (ESSET) which we developed for this purpose. (iii) We present a verification flow and use case example of mixed sync-async verification.…”
Section: B Contributionsmentioning
confidence: 99%