Xtensa: a configurable and extensible processor

Gonzalez, Ricardo E.

doi:10.1109/40.848473

Cited by 337 publications

(177 citation statements)

References 7 publications

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“…The simulations were performed with tools provided by Tensilica, Inc., for their configurable Xtensa processor core [7]. Using the Tensilica Instruction Extension (TIE) language, the proposed vldecode instruction from Section 2 was added to the instruction set, along with other instructions to set or obtain the contents of the group control register with M = 3.…”

Section: Performance Results From Simulationmentioning

confidence: 99%

Enhanced Architectural Support for Variable-Length Decoding

Sinnathamby¹,

Sudharsanan

Manjikian

2006

2006 IEEE International Conference on Multimedia and Expo

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This paper proposes a new architecture for efficient variable-length decoding (VLD) of entropy-coded data for multimedia applications on general-purpose processors. It improves on earlier proposals for low-complexity performance-enhancing hardware structures that exploit prefix/suffix properties of variable-length codes for common multimedia formats [1]. The enhanced architecture is compared to the previous architectures in terms of complexity and operating speed for FPGA implementation, and also in terms of area requirements, power consumption, and operating speed for a 0.18-µm ASIC fabrication process. Simulation results are reported for a pipelined processor with caches executing MPEG-4 software where VLD performance is doubled by incorporating the proposed architecture.

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Section: Performance Results From Simulationmentioning

confidence: 99%

Enhanced Architectural Support for Variable-Length Decoding

Sinnathamby¹,

Sudharsanan

Manjikian

2006

2006 IEEE International Conference on Multimedia and Expo

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“…While this approach has been shown to be effective in early studies, there are concerns for the amount of powercontrol instructions being added to programs with the increasing amount of components equipped with power-gating control in a SoC design platform for embedded systems. Note that architecture designers can custom the processor with unique operation functions [7,9,21]. Examples of these modules are abundant.…”

Section: Introductionmentioning

confidence: 99%

A sink-n-hoist framework for leakage power reduction

You

Huang

Lee

2005

Proceedings of the 5th ACM International Conference on Embedded Software

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Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts have tried to integrate architecture and compiler solutions to employ power-gating mechanisms to reduce leakage power. This approach is to have compilers perform data-flow analysis and insert instructions at programs to shut down and wake up components whenever appropriate for power reductions. While this approach has been shown to be effective in early studies, there are concerns for the amount of power-control instructions being added to programs with the increasing amount of components equipped with power-gating control in a SoC design platform. In this paper, we present a Sink-N-Hoist framework in the compiler solution to generate balanced scheduling of power-gating instructions. Our solution will attempt to merge power-gating instructions as one compound instruction. Therefore, it will reduce the amount of power-gating instructions issued. We perform experiments by incorporating our compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumptions on Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing the amount of power-gating instructions while further in reducing leakage power compared to previous methods.

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“…An application specific instruction set processor (ASIP) [7] tool generates a processor description with hardware support for user functions. The speedup from these can eliminate the need for a cache.…”

Section: Introductionmentioning

confidence: 99%