YaskSite: Stencil Optimization Techniques Applied to Explicit ODE Methods on Modern Architectures

Alappat, Christie L.; Seiferth, Johannes; Hager, Georg; Korch, Matthias; Rauber, Thomas; Wellein, Gerhard

doi:10.1109/cgo51591.2021.9370316

Cited by 2 publications

(2 citation statements)

References 31 publications

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“…Real caches, such as on the A64FX, have finite associativity and might only implement a pseudo‐LRU policy. However, it has been shown in References 11,29 that for most stencil codes these assumptions do not hamper the quality of the predictions. For simplicity we assume in the following that the lattice is sufficiently large such that the working set does not fit into cache.…”

Section: Case Study: Lattice Qcd Dw Kernelmentioning

confidence: 99%

Execution‐Cache‐Memory modeling and performance tuning of sparse matrix‐vector multiplication and Lattice quantum chromodynamics on A64FX

Alappat

Meyer

Laukemann

et al. 2021

Concurrency and Computation

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The A64FX CPU is arguably the most powerful Arm-based processor design to date.Although it is a traditional cache-based multicore processor, its peak performance and memory bandwidth rival accelerator devices. A good understanding of its performance features is of paramount importance for developers who wish to leverage its full potential. We present an architectural analysis of the A64FX used in the Fujitsu FX1000 supercomputer at a level of detail that allows for the construction of Execution-Cache-Memory performance models for steady-state loops. In the process we identify architectural peculiarities that point to viable generic optimization strategies. After validating the model using simple streaming loops we apply the insight gained to sparse matrix-vector multiplication (SpMV) and the domain wall (DW) kernel from quantum chromodynamics. For SpMV we show why the compressed row storage (CRS) matrix storage format is not a good practical choice on this architecture and how the SELL-C-𝜎 format can achieve bandwidth saturation. For the DW kernel we provide a cache-reuse analysis and show how an appropriate choice of data layout for complex arrays can realize memory-bandwidth saturation in this case as well. A comparison with state-of-the-art high-end Intel Cascade Lake AP and Nvidia V100 systems puts the capabilities of the A64FX into perspective. We also explore the potential for power optimizations using the tuning knobs provided by the Fugaku system, achieving energy savings of about 31% for SpMV and 18% for DW.

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Section: Case Study: Lattice Qcd Dw Kernelmentioning

confidence: 99%

Execution‐Cache‐Memory modeling and performance tuning of sparse matrix‐vector multiplication and Lattice quantum chromodynamics on A64FX

Alappat

Meyer

Laukemann

et al. 2021

Concurrency and Computation

Self Cite

View full text Add to dashboard Cite

show abstract

“…Real caches, such as on the A64FX, have finite associativity and might only implement a pseudo-LRU policy. However, it has been shown in [11,29] that for most stencil codes these assumptions do not hamper the quality of the predictions. For simplicity we assume in the following that the lattice is sufficiently large such that the working set does not fit into cache.…”

Section: Layer Conditionsmentioning

confidence: 99%

ECM modeling and performance tuning of SpMV and Lattice QCD on A64FX

Alappat,

Meyer,

Laukemann

et al. 2021

Preprint

Self Cite

View full text Add to dashboard Cite

The A64FX CPU is arguably the most powerful Arm-based processor design to date.Although it is a traditional cache-based multicore processor, its peak performance and memory bandwidth rival accelerator devices. A good understanding of its performance features is of paramount importance for developers who wish to leverage its full potential. We present an architectural analysis of the A64FX used in the Fujitsu FX1000 supercomputer at a level of detail that allows for the construction of Execution-Cache-Memory (ECM) performance models for steady-state loops. In the process we identify architectural peculiarities that point to viable generic optimization strategies. After validating the model using simple streaming loops we apply the insight gained to sparse matrix-vector multiplication (SpMV) and the domain wall (DW) kernel from quantum chromodynamics (QCD). For SpMV we show why the CRS matrix storage format is not a good practical choice on this architecture and how the SELL--format can achieve bandwidth saturation. For the DW kernel we provide a cache-reuse analysis and show how an appropriate choice of data layout for complex arrays can realize memory-bandwidth saturation in this case as well. A comparison with state-of-the-art high-end Intel Cascade Lake AP and Nvidia V100 systems puts the capabilities of the A64FX into perspective. We also explore the potential for power optimizations using the tuning knobs provided by the Fugaku system, achieving energy savings of about 31% for SpMV and 18% for DW.

show abstract

YaskSite: Stencil Optimization Techniques Applied to Explicit ODE Methods on Modern Architectures

Cited by 2 publications

References 31 publications

Execution‐Cache‐Memory modeling and performance tuning of sparse matrix‐vector multiplication and Lattice quantum chromodynamics on A64FX

Execution‐Cache‐Memory modeling and performance tuning of sparse matrix‐vector multiplication and Lattice quantum chromodynamics on A64FX

ECM modeling and performance tuning of SpMV and Lattice QCD on A64FX

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