Yet another spur mechanism in a charge-pump based Fractional-N PLL

Marnane, Aidan; Marotta, Valerio; Kennedy, Michael Peter

doi:10.1109/icecs.2016.7841236

Cited by 4 publications

(2 citation statements)

References 6 publications

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“…When the modulator's full cycle is completed, the fractional part is obtained on an average of the feedback divider ratio. The feedback divider ratio of a fractional PLL can be expressed as in (5) and (6),…”

Section: Integer Pll Architecturementioning

confidence: 99%

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Design of a spurious-free RF frequency synthesizer for fast-settling receivers

Yilmaz¹,

Topaloglu²

2020

Turk J Elec Eng & Comp Sci

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A tunable reference clock frequency topology is presented as a spur reduction application for frequency synthesizers of fast frequency hopping spread spectrum systems. The method was verified by measurements on a designed hardware operating at L-band frequencies. This spur reduction method is based on optimizing the reference clock frequency of synthesizers to mitigate spurs. By using the spur reduction method, the power of spurious signals was reduced up to 57 dB. The performance of the spur reduction method was also analyzed at different loop-filter configurations. Smaller lock time was obtained by enlarging the bandwidth of the loop filter up to 150 kHz. The required power response of the spurious signals specified in telecommunication standards was achieved even though the loop filter bandwidth was enlarged.

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Section: Integer Pll Architecturementioning

confidence: 99%

“…Based on the operation, several different reference clocks are required to obtain a proper spurious reduction, especially for very small step sizes. [3][4][5]…”

Section: Spurious-free Synthesizer Designmentioning

confidence: 99%