Yield and speed optimization of a latch-type voltage sense amplifier

Wicht, Bernhard; Nirschl, T.; Schmitt‐Landsiedel, D.

doi:10.1109/jssc.2004.829399

Cited by 418 publications

(209 citation statements)

References 15 publications

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“…The inverter is added as a separate additional gain stage and isolates any load capacitance from differential amplifier [7] In summary, the preamplifier based comparator offers high speed and less offset voltage but huge static power consumption. Fig-4 A Latch Type Voltage Sense Amplifier [1,2].…”

Section: Definitionmentioning

confidence: 99%

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High Speed Comparators for Analog-To-Digital Converter

Mandal¹,

Kumar²

2014

IOSRJEEE

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Section: Definitionmentioning

confidence: 99%

“…Extra switching transistors M10 and M11 are added to increase its characteristics. These circuits are used in sense amplifier based flip-flop, current-sensed SRAM [2]. …”

Section: B Fully Dynamic Latch Based Comparatorsmentioning

confidence: 99%

High Speed Comparators for Analog-To-Digital Converter

Mandal¹,

Kumar²

2014

IOSRJEEE

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“…1 (c) shows the schematic of the sense amplifier. Compared to conventional latch-type sense amplifiers, this one has a high-impedance input differential stage [8]. An input dc voltage of about 0.85 VDD is chosen here considering the tradeoff between power, area and system's reliability.…”

Section: B Fully Shareable and Symmetry Cell Layoutmentioning

confidence: 99%

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS

Han

Zhang

et al. 2012

IEICE Electron. Express

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This paper details the design of a 64 × 32 bit 4-read 2-write register file in TSMC 65 nm LP process. The register file avoids cell banking with pseudo-differential sensing scheme. Moreover, this approach enables a fully shareable and completely symmetry cell layout which shows competitive area results. Non-full-swing technique is proposed to avoid over design and improve energy efficiency. As for the timing control module, clocked pull-down circuit cuts off a possible short-current path at high clock frequency. A prototype is implemented in TSMC 65 nm LP technology. The measured results demonstrate operation of 0.77 GHz, consuming 7.08 mW at 1.2 V, and occupying 0.018 mm 2 .

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“…The ADC mainly consists of a bootstrapped-switch sampling front-end, a reference ladder for reference generation, 16 dynamic comparators (CMP), 45 SR-latches which are interpolated between every two adjacent CMPs' output, a digital encoder and a digital offset calibration circuit for the dynamic comparators. The architecture of CMP is StrongArm with NMOS transistors as the inputs [13] plus an extra input pair for calibrating its offset voltage. The calibration procedure is similar as [14].…”

Section: Introductionmentioning

confidence: 99%