Yield-Aware Cache Architectures

Özdemir, Serkan; Sinha, Debjit; Memik, Gokhan; Adams, Jonathan; Zhou, Hai

doi:10.1109/micro.2006.52

Cited by 75 publications

(57 citation statements)

References 21 publications

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“…Several researchers have proposed microarchitectural techniques to mitigate or tolerate parameter variation. They target register file and execution units [16], data caches [20], pipeline balancing [28], intelligent floorplanning [7] and core-to-core variation in power [3]. Other work proposed variation-aware thread scheduling [27] to exploit core-to-core variability.…”

Section: Related Workmentioning

confidence: 99%

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

BachaAnys

TeodorescuRadu

2013

SIGARCH Comput. Archit. News

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Lowering supply voltage is one of the most effective approaches for improving the energy efficiency of microprocessors. Unfortunately, technology limitations, such as process variability and circuit aging, are forcing microprocessor designers to add larger voltage guardbands to their chips. This makes supply voltage increasingly difficult to scale with technology. This paper presents a new mechanism for dynamically reducing voltage margins while maintaining the chip operating frequency constant. Unlike previous approaches that rely on special hardware to detect and recover from timing violations caused by low-voltage execution, our solution is firmware-based and does not require additional hardware. Instead, it relies on error correction mechanisms already built into modern processors. The system dynamically reduces voltage margins and uses correctable error reports raised by the hardware to identify the lowest, safe operating voltage. The solution adapts to core-to-core variability by tailoring supply voltage to each core's safe operating level. In addition, it exploits variability in workload vulnerability to low voltage execution. The system was prototyped on an HP Integrity Server that uses Intel's Itanium 9560 processors. Evaluation using SPECjbb2005 and SPEC CPU2000 workloads shows core power savings ranging from 18% to 23%, with minimal performance impact.

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Section: Related Workmentioning

confidence: 99%

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

BachaAnys

TeodorescuRadu

2013

SIGARCH Comput. Archit. News

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“…For memory dominated structures, the SRAM array lookups have significantly more regularity and allow for dynamic partitioning and resizing which may allow them to improve performance in an energy-efficient manner by sacrificing capacity [30]. There has been a significant amount of work in adapting SRAM structures for use in both lowvoltage modes and severe parameter variation [25,30,31]. In contrast, logic dominated structures in the processor backend, most notably execution units, would be difficult to accelerate without significant impact to the power budget.…”

Section: Background and Motivationmentioning

confidence: 99%

Identifying and predicting timing-critical instructions to boost timing speculation

Xin¹,

Joseph²

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins and eliminating power/performance overheads. Recent work has proposed microarchitectural methods to dynamically detect and recover from timing errors in processor logic. To a large extent existing work has relied on statistical error models and has not evaluated potential disparity of error rates at the level of static instructions. In this paper, we analyze gatelevel hardware models for an execution pipeline and demonstrate pronounced locality in instruction-level error rates due to value locality and data dependences. We propose timing error prediction to dynamically anticipate timing errors at the instruction-level and error padding techniques to avoid the full recovery cost of timing errors. We show that with simple prediction strategies our mechanism can reduce 80% of the performance penalty incurred by error recovery on average. This allows us to alleviate some limitations of timing speculation and improves energy-efficiency by 21% when compared to baseline timing speculation techniques using the same dynamic adaptive tuning mechanism.

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“…In sub-90nm designs as leakage can play a very important role, it was shown that in addition to considering latency cutoff, caches that consume leakage power greater than 3µ should also be rejected [21].…”

Section: B Evaluating Yieldmentioning

confidence: 99%

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

Ganapathy

Canal

González

et al. 2011

2011 IEEE 29th International Conference on Computer Design (ICCD)

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Abstract-In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations. Front body biasing (FBB) is employed for active sub-arrays to speed up accesses while inactive sub-arrays are reverse body biased (RBB) to reduce standby leakage power. Cache subarrays are classified based on run-time leakage and latency distributions and applied bias voltage is updated to account for these changes. This ensures that under all scenarios, the cache will consume the lowest leakage power for the target access latency computed at design-time. The backbone of the hardware used for classification is the 3T1D DRAM cell embedded into conventional 6T based memory. By measuring the access and retention time of the 3T1D cell, we show that it is possible to classify cache arrays based on run-time latency/leakage measurements. The tremendous increase in energy in active mode by forward biasing (to meet latency requirements) is compensated by reverse biasing inactive arrays. Our technique reduces leakage energy consumption and access latency of the cache on average by 20% & 18% respectively when compared to other state-of-the-art proposals. Finally we show that our technique will improve parametric yield by a maximum of 38% for worst-case scenario.

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Yield-Aware Cache Architectures

Cited by 75 publications

References 21 publications

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

Identifying and predicting timing-critical instructions to boost timing speculation

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

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