Yield modelling and analysis of bundled data and ring‐oscillator based designs

Abstract

Both ring-oscillator based clocks and bundled-data designs mitigate the ill effects of process, voltage, and temperature (PVT) variations. They both rely on delay lines which, when made post-silicon tunable, offer the opportunity to add test margin into the design in which the delay line in shipped products is set slower than that which is successfully tested. By adopting the uniform and per-chip test margin methods to asynchronous designs, this paper mathematically analyzes the resulting yield and shipped product quality loss and compares them to traditional synchronous design, quantifying the potential benefits that arise from the correlation in delay among paths in the delay line and combinational logic.

An FPGA Compliant Single-Rail Encoded Asynchronous Pipeline

“…The single-rail encoding scheme necessitates the placement of a delay element, typically an inverter chain or a counter, in the Req line to slow down request signals to match the speed of the datapath. This may also be necessary in the Ack line to meet the hold time requirements of interstage latches [10]. The delay-element placement might not work as the auto Place-And-Route (PAR) tools are unaware of asynchronous design methodology [11]; therefore, they do not preserve the delay ratios between control and various nets of datapaths [12].…”