You Only Traverse Twice: A YOTT Placement, Routing, and Timing Approach for CGRAs

Abstract

Coarse-grained reconfigurable architecture (CGRA) mapping involves three main steps: placement, routing, and timing. The mapping is an NP-complete problem, and a common strategy is to decouple this process into its independent steps. This work focuses on the placement step, and its aim is to propose a technique that is both reasonably fast and leads to high-performance solutions. Furthermore, a near-optimal placement simplifies the following routing and timing steps. Exact solutions cannot find placements in a reasonable execution time as input designs increase in size. Heuristic solutions include meta-heuristics, such as Simulated Annealing (SA) and fast and straightforward greedy heuristics based on graph traversal. However, as these approaches are probabilistic and have a large design space, it is not easy to provide both run-time efficiency and good solution quality. We propose a graph traversal heuristic that provides the best of both: high-quality placements similar to SA and the execution time of graph traversal approaches. Our placement introduces novel ideas based on “you only traverse twice” (YOTT) approach that performs a two-step graph traversal. The first traversal generates annotated data to guide the second step, which greedily performs the placement, node per node, aided by the annotated data and target architecture constraints. We introduce three new concepts to implement this technique: I/O and reconvergence annotation, degree matching, and look-ahead placement. Our analysis of this approach explores the placement execution time/quality trade-offs. We point out insights on how to analyze graph properties during dataflow mapping. Our results show that YOTT is 60.6 , 9.7 , and 2.3 faster than a high-quality SA, bounding box SA VPR, and multi-single traversal placements, respectively. Furthermore, YOTT reduces the average wire length and the maximal FIFO size (additional timing requirement on CGRAs) to avoid delay mismatches in fully pipelined architectures.

Algoritmos de Posicionamento e Roteamento baseados em Travessia de Grafo para Arquiteturas Reconfiguráveis de Grão Grosso (CGRA)

“…A ferramenta VPR [Murray and et al 2020] gerou uma soluc ¸ão pior do que o Z1000 e a implementac ¸ão GPU. A Tabela 2 compara a acelerac ¸ão no tempo de execuc ¸ão e a qualidade da soluc ¸ão dos algoritmos múltipla travessia (YOTO) [Canesche et al 2020] e YOLT [Canesche et al 2021] com o VPR [Murray and et al 2020]. Os resultados estão normalizados em relac ¸ão ao VPR Bound Box.…”

“…A quinta contribuic ¸ão foi a poda no espac ¸o de busca da das escolhas no CGRA com a verificac ¸ão do grau dos vértices e uma pré-validac ¸ão do posicionamento na proximidade de uma reconvergência, chamada de lookahead. O algoritmo de dupla travessia foi publicado no período ACM Transactions on Embedded Computing Systems [Canesche et al 2021]. A sexta contribuic ¸ão foram a implementac ¸ão do roteamento e de escalonamento.…”

Design exploration of machine learning data-flows onto heterogeneous reconfigurable hardware

“…Heuristic approaches provide approximate solutions and scalability without the guarantee of optimality. By employing techniques such as local search based on graph level (Ferreira et al, 2005), genetic algorithms (Silva et al, 2006), graph traversal approaches (Canesche et al, 2020(Canesche et al, , 2021, or simulated annealing (Luu et al, 2011;Oliveira et al, 2020a), heuristics can efficiently explore large solution spaces and find good-quality solutions within reasonable time frames.…”