Zero Aliasing Space Compaction with Cellular Automata

Abstract

Complex integrated circuits produce voluminous test response ~a~a. S~ace. compacti~n reduces the space requirement to store the response data by combmmg c1rcurt outputs m certain fashion to reduce the number of outputs to be observed. In this paper, we present the design of a zero-aliasing space compactor that utilizes the theory of Cellular A~tomata based pattern classification to classify the fault-free and the faulty responses. Experimental results with the JSCAS85 benchmark circuits show that the scheme results in 1.26 time more compaction over the earlier zero-aliasing space compaction strategies. Area overhead of the proposed scheme is also much lesser.