Zero Defectivity Dual Gate Processing

Abstract

A mixed-signal automotive device manufactured in a dual gate process historically had sporadic yields. Problems were associated with analog failures, including the temperature sense circuit, load dump trip levels, comparators and the 8MHz oscillator. These issues related to p-mos devices with common mode inputs <1.5V. The only anomaly observed at electrical test was in the threshold voltage matching of a particular size of transistor pairs. When 100% testing of these scribe line monitors was performed there were many random failures, with higher probability around the perimeter of the wafer. The magnitude of the offset was consistent with a 2nm difference in gate oxide thickness. Darkfield inspection following etchback of oxide from standard gate regions showed water spotting and damage to active areas. No defects were observed following the introduction of a 10sec oxygen plasma treatment prior to oxide etchback. This change coincided with improved yields and the elimination of the analog failures.

Integration Challenges in Standard CMOS with Multiple Gate Oxide Thicknesses

“…The damage was in a pattern similar to the patter of the Vt anomaly and consistent with the method of oxide etch back. Process changes were implemented to minimize this damage [4]. Subsequent lots yielded well and matching problems were eliminated.…”

“…One way that we have conquered this challenge is by developing an additional thick gate in a 0.5µm single gate process technology [4]. This allowed circuit designers the flexibility for Vg at car battery potential.…”