Zero power 4.95Gbps HDMI transmitter

Gupta, Nitin; Nandy, Tapas; Sahni, Paramjeet Singh; Garg, Manish; Tripathi, Jai Narayan

doi:10.1109/iscas.2014.6865431

Cited by 1 publication

(2 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus four pre-driver channels were used. This even and odd period driving has the advantage of hiding data-dependent surges on supply nets which arise due to pre-driver switching [2]. The pre-driver outputs were applied to the driving circuit as shown in Fig.…”

Section: Hdmi Transmitter Data Channelmentioning

confidence: 99%

“…This normally results in increased design and fabrication cost of the devices. While some other designs use reduced signal swing of the output voltage which do not apply to the presented target interface [2][3][4][5][6]. This design presents the data channel section of the HDMI transmitter circuit in 180 nm CMOS which is input with only one frequency of serial clock coming from the PLL and eliminated the use of multiple clock signals [7].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design of a Low-Power 1.65 GBPS Data Channel for HDMI Transmitter

Agrawal¹,

Gamad²

2015

VLSICS

View full text Add to dashboard Cite

This paper presents a design of low power data channel for application in High Definition MultimediaInterface (HDMI) Transmitter circuit. The input is 10 bit parallel data and output is serial data at 1.65 Gbps. This circuit uses only a single frequency of serial clock input. All other timing signals are derived within the circuit from the serial clock. This design has dedicated lines to disable and enable all its channels within two pixel-clock periods only. A pair of disable and enable functions performed immediately after power-on of the circuit serves as the reset function. The presented design is immune to data-dependent switching spikes in supply current and pushes them in the range of serial frequency and its multiples. Thus filtering requirements are relaxed. The output stage uses a bias voltage of 2.8 volts for a receiver pull-up voltage of 3.3 volts. The reported data channel is designed using UMC 180 nm CMOS Technology. The design is modifiable for other inter-board serial interfaces like USB and LAN with different number of bits at the parallel input.

show abstract

Section: Hdmi Transmitter Data Channelmentioning

confidence: 99%