In today's electronic sector, low energy has appeared as a major feature. Power effectiveness is one of the most significant characteristics of contemporary, high-speed and mobile digital devices. Different methods are available to decrease energy dissipation at distinct stages of the planning method and have been applied. As the transistors count per device region continues to rise, while the switching energy does not rise at the same pace, power dissipation increases, and heat removal becomes more hard and costly. The power consumption of electronic appliances can be decreased by using various logic types. For such low-power electronic applications, adiabatic logic mode is very appealing. Using adiabatic logic, distinct powerefficient gates are intended in this document and contrasted for energy dissipation, propagation delay and no of the transistors used. In addition, the circuit developer can use these gates in the combinational and sequential circuits to develop low-power systems. The simulations of these gates are carried out in 90 nm technology using cadence virtuoso instrument.