Two separate goals should be jointly pursued in wastewater treatment: nutrient removal and energy conservation. An efficient controller performance should cope with process uncertainties, seasonal variations and process nonlinearities. This paper describes the design and testing of a model predictive controller (MPC) based on neuro-fuzzy techniques that is capable of estimating the main process variables and providing the right amount of aeration to achieve an efficient and economical operation. This algorithm has been field tested on a large-scale municipal wastewater treatment plant of about 500,000 PE, with encouraging results in terms of better effluent quality and energy savings.

a b s t r a c tIn the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10215 mm in both coordinates, low material budget o 1%X 0 , and the ability to withstand a background hit rate of several tens of MHz=cm 2 . Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time

a b s t r a c tThe baseline detector option for the first layer of the SuperB Silicon Vertex Tracker (SVT) is a high resistivity double-sided silicon device with short strips (striplets) at 451 angle to the detector's edge. A prototype was tested with a 120 GeV/c pion beam in September 2011 at the SPS-H6 test-beam line at CERN. In this paper studies on efficiency, resolution and cluster size are reported.

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The asymmetric e(+) e(-) collider SuperB is designed to deliver a high luminosity, greater than 10(36) cm(-2) S-1, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%. (C) 2012 Elsevier B.V. All rights reserved