The DP(Double-Precision) floating-point multiplier require a bulky 52x52 mantissa multiplications. The enactment of the DP floating number multiplication predominantlybe influenced by on the area and speed. This paper presents a improveduniquemethod to diminution this huge multiplicationpracticeof mantissa. The UTmethodpermitsusinga reducedquantityof multiplication hardware equaled to the conventional method. In old-fashionedschemeaccumulation of the partial products are independentlycompleted and it may perhapsyieldextraperiod of time in contrast to thesuggested method. In the suggestedprocess the partial products are parallel added with the multiplication actions and it canreduce the time delay. The method wasinstigated using VerilogHDL with Xilinx 14.2 ISE tools on Virtex-5 FPGA.