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The desire for persistent, long term surveillance and covertness places severe constraints on the power consumption of a sensor node. To achieve the desired endurance while minimizing the size of the node, it is imperative to use application-specific integrated circuits (ASICs) that deliver the required performance with maximal power efficiency while minimizing the amount of communication bandwidth needed. This paper reviews our ongoing effort to integrate several micropower devices for low-power wake-up detection, blind source separation and localization and pattern classification, and demonstrate the utility of the system in relevant surveillance applications. The capabilities of each module are presented in detail along with performance statistics measured during recent experiments.

A mixed-signal adaptive VLSI architecture for real-time blind separation of linear source mixtures is presented. The architecture is digitally reconfigurable and implements a general class of Independent Component Analysis (ICA) update rules in common outer-product form. In conjunction with gradient flow, a technique for converting timedelayed mixtures of traveling wave sources into equivalent linear instantaneous mixtures by observing spatial and temporal derivatives of the field over a miniature array, the ICA architecture allows to separate and localize multiple acoustic sources in the acoustic scene. Experimental results from VLSI implementation of the ICA architecture demonstrate 30 dB separation of two mixtures of two speech signals.

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In this paper, we present a fast algorithm to derive the iii harmonic distortion in fully balanced Gm -C filters. It is based on Vi i state-space modeling and decomposition of the filter into a cascade g11 of an input stage, a core stage and an output stage. This approach _results in compact expressions for the distortion that involve explicitly the structural matrices of the filter and the values of the circuit elements. The algorithm was verified using a third-order low pass Butterworth filter designed in a 0.5,um CMOS process. The theoretical results are found to be in good agreement with CADENCE and MATLAB simulations. Fig. 1. The basic Gm-C block.