We present a simple method for the elimination of cracks in GaN layers grown on Si (111). Cracking of GaN on Si usually occurs due to large lattice and thermal mismatch of GaN and Si when layer thicknesses exceeds approximately 1 µm. By introducing thin, low-temperature AlN interlayers, we could significantly reduce the crack density of the GaN layer. The crack density is practically reduced to zero from an original crack density of 240 mm-2 corresponding to crack-free regions of 3×10-3 mm2. Additionally for the GaN layer with low temperature interlayers, the full width at half maximum X-ray (2024) rocking curve is improved from approximately 270 to 65 arcsec.

Spatially separated ZnO pillars, typically 300 nm in diameter and 2 microm in height, are fabricated via a template-directed approach that leads to long-range hexagonal order. The templates of Au nanodisk arrays are obtained by using metal membranes as a lithography mask. The growth of ZnO pillars is performed in a double-tube system through vapor diffusion-deposition. The growth mechanism of the pillars is studied in detail and is proposed to be a combination of vapor-liquid-solid and vapor-solid models. The piezoelectric and optical properties of single pillars are characterized using piezoresponse force microscopy and micro-photoluminescence spectroscopy, respectively. The pillars show strong excitonic emissions up to room temperature, which indicate a relatively low defect density and good crystalline quality. The obtained piezoelectric coefficient d(33) is (7.5+/-0.6) pm V(-1), which is to our knowledge the first reported value for a single nanopillar.

We report on GaN n-type doping using silane, germane, and isobutylgermane as Si and Ge dopants, respectively. A significant increase in tensile stress during growth is observed for Si doped samples while this is not the case for Ge doping. In addition, Ge can be doped up to 2.9 Â 10 20 cm À3 , while Si doping leads to 3-D growth already at concentrations around 1.9 Â 10 19 cm À3. The free carrier concentration was determined by Hall-effect measurements, crystal quality, and structural properties by x-ray diffraction measurements. Additionally, secondary ion mass spectroscopy and Raman measurements were performed demonstrating the high material quality of Ge doped samples. V

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Vertical gallium nitride (GaN) power devices have attracted increased attention due to their superior high-voltage and high-current capacity as well as easier thermal management than lateral GaN high electron mobility transistors. Vertical GaN devices are promising candidates for next-generation power electronics in electric vehicles, data centers, smart grids and renewable energy process. The use of low-cost foreign substrates such as silicon (Si) substrates, instead of the expensive free-standing GaN substrates, could greatly trim material cost and enable large-diameter wafer processing while maintaining high device performance. This review illustrates recent progress in material epitaxy, device design, device physics and processing technologies for the development of vertical GaN power devices on low-cost foreign substrates. Although the device technologies are still at the early stage of development, state-of-the-art vertical GaN-on-Si power diodes have already shown superior Baliga's figure of merit than commercial SiC and Si power devices at the voltage classes beyond 600 V. Furthermore, we unveil the design space of vertical GaN power devices on native and different foreign substrates, from the analysis of the impact of dislocation and defects on device performance. We conclude by identifying the application space, current challenges and exciting research opportunities in this very dynamic research field.