We report on a flexible 300 mm process that optimally combines optical and electron beam lithography to fabricate silicon spin qubits. It enables on-the-fly layout design modifications while allowing devices with either n-or p-type ohmic implants, a pitch smaller than 100 nm, and uniform critical dimensions down to 30 nm with a standard deviation ~ 1.6 nm.Various n-and p-type qubits are characterized in a dilution refrigerator at temperatures ~ 10 mK. Electrical measurements demonstrate well-defined quantum dots, tunable tunnel couplings, and coherent spin control, which are essential requirements for the implementation of a large-scale quantum processor.

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The quality of the semiconductor-barrier interface plays a pivotal role in the demonstration of high quality reproducible quantum dots for quantum information processing. In this work, we have measured SiMOSFET Hall bars on undoped Si substrates in order to investigate the device quality. For devices fabricated in a full CMOS process and of very thin oxide below a thickness of \unit[10]{nm}, we report a record mobility of \unit[$17.5\times 10^{3}$]{cm$^2$/Vs} indicating a high quality interface, suitable for future qubit applications. We also study the influence of gate materials on the mobilities and discuss the underlying mechanisms, giving insight into further material optimization for large scale quantum processors.